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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity AVALON_avalon_slave_arbitrator is 
        port (
              -- inputs:
                 signal AVALON_avalon_slave_irq : IN STD_LOGIC;
                 signal AVALON_avalon_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal AVALON_avalon_slave_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                 signal CPU_instruction_master_read : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal AVALON_avalon_slave_address : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal AVALON_avalon_slave_chipselect : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_irq_from_sa : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_read : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal AVALON_avalon_slave_waitrequest_from_sa : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_write : OUT STD_LOGIC;
                 signal AVALON_avalon_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_data_master_granted_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_data_master_requests_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_instruction_master_granted_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal CPU_instruction_master_requests_AVALON_avalon_slave : OUT STD_LOGIC;
                 signal d1_AVALON_avalon_slave_end_xfer : OUT STD_LOGIC;
                 signal registered_CPU_data_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of AVALON_avalon_slave_arbitrator : entity is FALSE;
end entity AVALON_avalon_slave_arbitrator;


architecture europa of AVALON_avalon_slave_arbitrator is
                signal AVALON_avalon_slave_allgrants :  STD_LOGIC;
                signal AVALON_avalon_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal AVALON_avalon_slave_any_continuerequest :  STD_LOGIC;
                signal AVALON_avalon_slave_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_arb_counter_enable :  STD_LOGIC;
                signal AVALON_avalon_slave_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_arbitration_holdoff_internal :  STD_LOGIC;
                signal AVALON_avalon_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal AVALON_avalon_slave_begins_xfer :  STD_LOGIC;
                signal AVALON_avalon_slave_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal AVALON_avalon_slave_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_end_xfer :  STD_LOGIC;
                signal AVALON_avalon_slave_firsttransfer :  STD_LOGIC;
                signal AVALON_avalon_slave_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_in_a_read_cycle :  STD_LOGIC;
                signal AVALON_avalon_slave_in_a_write_cycle :  STD_LOGIC;
                signal AVALON_avalon_slave_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_non_bursting_master_requests :  STD_LOGIC;
                signal AVALON_avalon_slave_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal AVALON_avalon_slave_slavearbiterlockenable :  STD_LOGIC;
                signal AVALON_avalon_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal AVALON_avalon_slave_waits_for_read :  STD_LOGIC;
                signal AVALON_avalon_slave_waits_for_write :  STD_LOGIC;
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register_in :  STD_LOGIC;
                signal CPU_data_master_saved_grant_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_instruction_master_continuerequest :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register_in :  STD_LOGIC;
                signal CPU_instruction_master_saved_grant_AVALON_avalon_slave :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_AVALON_avalon_slave_waitrequest_from_sa :  STD_LOGIC;
                signal internal_CPU_data_master_granted_AVALON_avalon_slave :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_AVALON_avalon_slave :  STD_LOGIC;
                signal internal_CPU_data_master_requests_AVALON_avalon_slave :  STD_LOGIC;
                signal internal_CPU_instruction_master_granted_AVALON_avalon_slave :  STD_LOGIC;
                signal internal_CPU_instruction_master_qualified_request_AVALON_avalon_slave :  STD_LOGIC;
                signal internal_CPU_instruction_master_requests_AVALON_avalon_slave :  STD_LOGIC;
                signal last_cycle_CPU_data_master_granted_slave_AVALON_avalon_slave :  STD_LOGIC;
                signal last_cycle_CPU_instruction_master_granted_slave_AVALON_avalon_slave :  STD_LOGIC;
                signal p1_CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register :  STD_LOGIC;
                signal p1_CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register :  STD_LOGIC;
                signal wait_for_AVALON_avalon_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT AVALON_avalon_slave_end_xfer;
      end if;
    end if;

  end process;

  AVALON_avalon_slave_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_CPU_data_master_qualified_request_AVALON_avalon_slave OR internal_CPU_instruction_master_qualified_request_AVALON_avalon_slave));
  --assign AVALON_avalon_slave_readdata_from_sa = AVALON_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  AVALON_avalon_slave_readdata_from_sa <= AVALON_avalon_slave_readdata;
  internal_CPU_data_master_requests_AVALON_avalon_slave <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 2) & std_logic_vector'("00")) = std_logic_vector'("100000001000100010011000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign AVALON_avalon_slave_waitrequest_from_sa = AVALON_avalon_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_AVALON_avalon_slave_waitrequest_from_sa <= AVALON_avalon_slave_waitrequest;
  --registered rdv signal_name registered_CPU_data_master_read_data_valid_AVALON_avalon_slave assignment, which is an e_assign
  registered_CPU_data_master_read_data_valid_AVALON_avalon_slave <= CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register_in;
  --AVALON_avalon_slave_arb_share_counter set values, which is an e_mux
  AVALON_avalon_slave_arb_share_set_values <= std_logic_vector'("01");
  --AVALON_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  AVALON_avalon_slave_non_bursting_master_requests <= ((internal_CPU_data_master_requests_AVALON_avalon_slave OR internal_CPU_instruction_master_requests_AVALON_avalon_slave) OR internal_CPU_data_master_requests_AVALON_avalon_slave) OR internal_CPU_instruction_master_requests_AVALON_avalon_slave;
  --AVALON_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  AVALON_avalon_slave_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(AVALON_avalon_slave_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (AVALON_avalon_slave_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(AVALON_avalon_slave_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (AVALON_avalon_slave_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --AVALON_avalon_slave_allgrants all slave grants, which is an e_mux
  AVALON_avalon_slave_allgrants <= ((or_reduce(AVALON_avalon_slave_grant_vector) OR or_reduce(AVALON_avalon_slave_grant_vector)) OR or_reduce(AVALON_avalon_slave_grant_vector)) OR or_reduce(AVALON_avalon_slave_grant_vector);
  --AVALON_avalon_slave_end_xfer assignment, which is an e_assign
  AVALON_avalon_slave_end_xfer <= NOT ((AVALON_avalon_slave_waits_for_read OR AVALON_avalon_slave_waits_for_write));
  --AVALON_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  AVALON_avalon_slave_arb_counter_enable <= ((AVALON_avalon_slave_end_xfer AND AVALON_avalon_slave_allgrants)) OR ((AVALON_avalon_slave_end_xfer AND NOT AVALON_avalon_slave_non_bursting_master_requests));
  --AVALON_avalon_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      AVALON_avalon_slave_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(AVALON_avalon_slave_arb_counter_enable) = '1' then 
        AVALON_avalon_slave_arb_share_counter <= AVALON_avalon_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --AVALON_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      AVALON_avalon_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((or_reduce(AVALON_avalon_slave_master_qreq_vector) AND AVALON_avalon_slave_end_xfer)) OR ((AVALON_avalon_slave_end_xfer AND NOT AVALON_avalon_slave_non_bursting_master_requests)))) = '1' then 
        AVALON_avalon_slave_slavearbiterlockenable <= or_reduce(AVALON_avalon_slave_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master AVALON/avalon_slave arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= AVALON_avalon_slave_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --AVALON_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  AVALON_avalon_slave_slavearbiterlockenable2 <= or_reduce(AVALON_avalon_slave_arb_share_counter_next_value);
  --CPU/data_master AVALON/avalon_slave arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= AVALON_avalon_slave_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --CPU/instruction_master AVALON/avalon_slave arbiterlock, which is an e_assign
  CPU_instruction_master_arbiterlock <= AVALON_avalon_slave_slavearbiterlockenable AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master AVALON/avalon_slave arbiterlock2, which is an e_assign
  CPU_instruction_master_arbiterlock2 <= AVALON_avalon_slave_slavearbiterlockenable2 AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master granted AVALON/avalon_slave last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_instruction_master_granted_slave_AVALON_avalon_slave <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_instruction_master_granted_slave_AVALON_avalon_slave <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_instruction_master_saved_grant_AVALON_avalon_slave) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((AVALON_avalon_slave_arbitration_holdoff_internal OR NOT internal_CPU_instruction_master_requests_AVALON_avalon_slave))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_instruction_master_granted_slave_AVALON_avalon_slave))))));
      end if;
    end if;

  end process;

  --CPU_instruction_master_continuerequest continued request, which is an e_mux
  CPU_instruction_master_continuerequest <= last_cycle_CPU_instruction_master_granted_slave_AVALON_avalon_slave AND internal_CPU_instruction_master_requests_AVALON_avalon_slave;
  --AVALON_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_mux
  AVALON_avalon_slave_any_continuerequest <= CPU_instruction_master_continuerequest OR CPU_data_master_continuerequest;
  internal_CPU_data_master_qualified_request_AVALON_avalon_slave <= internal_CPU_data_master_requests_AVALON_avalon_slave AND NOT (((((CPU_data_master_read AND (CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register))) OR (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write))) OR CPU_instruction_master_arbiterlock));
  --CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register_in <= ((internal_CPU_data_master_granted_AVALON_avalon_slave AND CPU_data_master_read) AND NOT AVALON_avalon_slave_waits_for_read) AND NOT (CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register);
  --shift register p1 CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register) & A_ToStdLogicVector(CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register_in)));
  --CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register <= p1_CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid CPU_data_master_read_data_valid_AVALON_avalon_slave, which is an e_mux
  CPU_data_master_read_data_valid_AVALON_avalon_slave <= CPU_data_master_read_data_valid_AVALON_avalon_slave_shift_register;
  --AVALON_avalon_slave_writedata mux, which is an e_mux
  AVALON_avalon_slave_writedata <= CPU_data_master_writedata;
  internal_CPU_instruction_master_requests_AVALON_avalon_slave <= ((to_std_logic(((Std_Logic_Vector'(CPU_instruction_master_address_to_slave(23 DOWNTO 2) & std_logic_vector'("00")) = std_logic_vector'("100000001000100010011000")))) AND (CPU_instruction_master_read))) AND CPU_instruction_master_read;
  --CPU/data_master granted AVALON/avalon_slave last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_data_master_granted_slave_AVALON_avalon_slave <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_data_master_granted_slave_AVALON_avalon_slave <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_data_master_saved_grant_AVALON_avalon_slave) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((AVALON_avalon_slave_arbitration_holdoff_internal OR NOT internal_CPU_data_master_requests_AVALON_avalon_slave))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_data_master_granted_slave_AVALON_avalon_slave))))));
      end if;
    end if;

  end process;

  --CPU_data_master_continuerequest continued request, which is an e_mux
  CPU_data_master_continuerequest <= last_cycle_CPU_data_master_granted_slave_AVALON_avalon_slave AND internal_CPU_data_master_requests_AVALON_avalon_slave;
  internal_CPU_instruction_master_qualified_request_AVALON_avalon_slave <= internal_CPU_instruction_master_requests_AVALON_avalon_slave AND NOT ((((CPU_instruction_master_read AND ((to_std_logic(((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_latency_counter)))))) OR (CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register))))) OR CPU_data_master_arbiterlock));
  --CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register_in <= (internal_CPU_instruction_master_granted_AVALON_avalon_slave AND CPU_instruction_master_read) AND NOT AVALON_avalon_slave_waits_for_read;
  --shift register p1 CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register) & A_ToStdLogicVector(CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register_in)));
  --CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register <= p1_CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid CPU_instruction_master_read_data_valid_AVALON_avalon_slave, which is an e_mux
  CPU_instruction_master_read_data_valid_AVALON_avalon_slave <= CPU_instruction_master_read_data_valid_AVALON_avalon_slave_shift_register;
  --allow new arb cycle for AVALON/avalon_slave, which is an e_assign
  AVALON_avalon_slave_allow_new_arb_cycle <= NOT CPU_data_master_arbiterlock AND NOT CPU_instruction_master_arbiterlock;
  --CPU/instruction_master assignment into master qualified-requests vector for AVALON/avalon_slave, which is an e_assign
  AVALON_avalon_slave_master_qreq_vector(0) <= internal_CPU_instruction_master_qualified_request_AVALON_avalon_slave;
  --CPU/instruction_master grant AVALON/avalon_slave, which is an e_assign
  internal_CPU_instruction_master_granted_AVALON_avalon_slave <= AVALON_avalon_slave_grant_vector(0);
  --CPU/instruction_master saved-grant AVALON/avalon_slave, which is an e_assign
  CPU_instruction_master_saved_grant_AVALON_avalon_slave <= AVALON_avalon_slave_arb_winner(0) AND internal_CPU_instruction_master_requests_AVALON_avalon_slave;
  --CPU/data_master assignment into master qualified-requests vector for AVALON/avalon_slave, which is an e_assign
  AVALON_avalon_slave_master_qreq_vector(1) <= internal_CPU_data_master_qualified_request_AVALON_avalon_slave;
  --CPU/data_master grant AVALON/avalon_slave, which is an e_assign
  internal_CPU_data_master_granted_AVALON_avalon_slave <= AVALON_avalon_slave_grant_vector(1);
  --CPU/data_master saved-grant AVALON/avalon_slave, which is an e_assign
  CPU_data_master_saved_grant_AVALON_avalon_slave <= AVALON_avalon_slave_arb_winner(1) AND internal_CPU_data_master_requests_AVALON_avalon_slave;
  --AVALON/avalon_slave chosen-master double-vector, which is an e_assign
  AVALON_avalon_slave_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((AVALON_avalon_slave_master_qreq_vector & AVALON_avalon_slave_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT AVALON_avalon_slave_master_qreq_vector & NOT AVALON_avalon_slave_master_qreq_vector))) + (std_logic_vector'("000") & (AVALON_avalon_slave_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  AVALON_avalon_slave_arb_winner <= A_WE_StdLogicVector((std_logic'(((AVALON_avalon_slave_allow_new_arb_cycle AND or_reduce(AVALON_avalon_slave_grant_vector)))) = '1'), AVALON_avalon_slave_grant_vector, AVALON_avalon_slave_saved_chosen_master_vector);
  --saved AVALON_avalon_slave_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      AVALON_avalon_slave_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(AVALON_avalon_slave_allow_new_arb_cycle) = '1' then 
        AVALON_avalon_slave_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(AVALON_avalon_slave_grant_vector)) = '1'), AVALON_avalon_slave_grant_vector, AVALON_avalon_slave_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  AVALON_avalon_slave_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((AVALON_avalon_slave_chosen_master_double_vector(1) OR AVALON_avalon_slave_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((AVALON_avalon_slave_chosen_master_double_vector(0) OR AVALON_avalon_slave_chosen_master_double_vector(2)))));
  --AVALON/avalon_slave chosen master rotated left, which is an e_assign
  AVALON_avalon_slave_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(AVALON_avalon_slave_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(AVALON_avalon_slave_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --AVALON/avalon_slave's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      AVALON_avalon_slave_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(AVALON_avalon_slave_grant_vector)) = '1' then 
        AVALON_avalon_slave_arb_addend <= A_WE_StdLogicVector((std_logic'(AVALON_avalon_slave_end_xfer) = '1'), AVALON_avalon_slave_chosen_master_rot_left, AVALON_avalon_slave_grant_vector);
      end if;
    end if;

  end process;

  AVALON_avalon_slave_chipselect <= internal_CPU_data_master_granted_AVALON_avalon_slave OR internal_CPU_instruction_master_granted_AVALON_avalon_slave;
  --AVALON_avalon_slave_firsttransfer first transaction, which is an e_assign
  AVALON_avalon_slave_firsttransfer <= NOT ((AVALON_avalon_slave_slavearbiterlockenable AND AVALON_avalon_slave_any_continuerequest));
  --AVALON_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  AVALON_avalon_slave_beginbursttransfer_internal <= AVALON_avalon_slave_begins_xfer AND AVALON_avalon_slave_firsttransfer;
  --AVALON_avalon_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  AVALON_avalon_slave_arbitration_holdoff_internal <= AVALON_avalon_slave_begins_xfer AND AVALON_avalon_slave_firsttransfer;
  --AVALON_avalon_slave_read assignment, which is an e_mux
  AVALON_avalon_slave_read <= ((internal_CPU_data_master_granted_AVALON_avalon_slave AND CPU_data_master_read)) OR ((internal_CPU_instruction_master_granted_AVALON_avalon_slave AND CPU_instruction_master_read));
  --AVALON_avalon_slave_write assignment, which is an e_mux
  AVALON_avalon_slave_write <= internal_CPU_data_master_granted_AVALON_avalon_slave AND CPU_data_master_write;
  --AVALON_avalon_slave_address mux, which is an e_mux
  AVALON_avalon_slave_address <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_AVALON_avalon_slave)) = '1'), (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010"))), (A_SRL(CPU_instruction_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")))));
  --d1_AVALON_avalon_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_AVALON_avalon_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_AVALON_avalon_slave_end_xfer <= AVALON_avalon_slave_end_xfer;
      end if;
    end if;

  end process;

  --AVALON_avalon_slave_waits_for_read in a cycle, which is an e_mux
  AVALON_avalon_slave_waits_for_read <= AVALON_avalon_slave_in_a_read_cycle AND internal_AVALON_avalon_slave_waitrequest_from_sa;
  --AVALON_avalon_slave_in_a_read_cycle assignment, which is an e_assign
  AVALON_avalon_slave_in_a_read_cycle <= ((internal_CPU_data_master_granted_AVALON_avalon_slave AND CPU_data_master_read)) OR ((internal_CPU_instruction_master_granted_AVALON_avalon_slave AND CPU_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= AVALON_avalon_slave_in_a_read_cycle;
  --AVALON_avalon_slave_waits_for_write in a cycle, which is an e_mux
  AVALON_avalon_slave_waits_for_write <= AVALON_avalon_slave_in_a_write_cycle AND internal_AVALON_avalon_slave_waitrequest_from_sa;
  --AVALON_avalon_slave_in_a_write_cycle assignment, which is an e_assign
  AVALON_avalon_slave_in_a_write_cycle <= internal_CPU_data_master_granted_AVALON_avalon_slave AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= AVALON_avalon_slave_in_a_write_cycle;
  wait_for_AVALON_avalon_slave_counter <= std_logic'('0');
  --AVALON_avalon_slave_byteenable byte enable port mux, which is an e_mux
  AVALON_avalon_slave_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_AVALON_avalon_slave)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (CPU_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --assign AVALON_avalon_slave_irq_from_sa = AVALON_avalon_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  AVALON_avalon_slave_irq_from_sa <= AVALON_avalon_slave_irq;
  --vhdl renameroo for output signals
  AVALON_avalon_slave_waitrequest_from_sa <= internal_AVALON_avalon_slave_waitrequest_from_sa;
  --vhdl renameroo for output signals
  CPU_data_master_granted_AVALON_avalon_slave <= internal_CPU_data_master_granted_AVALON_avalon_slave;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_AVALON_avalon_slave <= internal_CPU_data_master_qualified_request_AVALON_avalon_slave;
  --vhdl renameroo for output signals
  CPU_data_master_requests_AVALON_avalon_slave <= internal_CPU_data_master_requests_AVALON_avalon_slave;
  --vhdl renameroo for output signals
  CPU_instruction_master_granted_AVALON_avalon_slave <= internal_CPU_instruction_master_granted_AVALON_avalon_slave;
  --vhdl renameroo for output signals
  CPU_instruction_master_qualified_request_AVALON_avalon_slave <= internal_CPU_instruction_master_qualified_request_AVALON_avalon_slave;
  --vhdl renameroo for output signals
  CPU_instruction_master_requests_AVALON_avalon_slave <= internal_CPU_instruction_master_requests_AVALON_avalon_slave;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_data_master_granted_AVALON_avalon_slave))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_instruction_master_granted_AVALON_avalon_slave))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line, now);
          write(write_line, string'(": "));
          write(write_line, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line.all);
          deallocate (write_line);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line1 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_data_master_saved_grant_AVALON_avalon_slave))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_saved_grant_AVALON_avalon_slave))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line1, now);
          write(write_line1, string'(": "));
          write(write_line1, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line1.all);
          deallocate (write_line1);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity NIOS_II_reset_clk_90_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity NIOS_II_reset_clk_90_domain_synch_module;


architecture europa of NIOS_II_reset_clk_90_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity CPU_jtag_debug_module_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_debugaccess : IN STD_LOGIC;
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                 signal CPU_instruction_master_read : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                 signal CPU_jtag_debug_module_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_jtag_debug_module_resetrequest : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_data_master_requests_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_instruction_master_granted_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_instruction_master_requests_CPU_jtag_debug_module : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal CPU_jtag_debug_module_begintransfer : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_jtag_debug_module_chipselect : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_debugaccess : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_jtag_debug_module_reset : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_reset_n : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_resetrequest_from_sa : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_write : OUT STD_LOGIC;
                 signal CPU_jtag_debug_module_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_CPU_jtag_debug_module_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of CPU_jtag_debug_module_arbitrator : entity is FALSE;
end entity CPU_jtag_debug_module_arbitrator;


architecture europa of CPU_jtag_debug_module_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_instruction_master_continuerequest :  STD_LOGIC;
                signal CPU_instruction_master_saved_grant_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_jtag_debug_module_allgrants :  STD_LOGIC;
                signal CPU_jtag_debug_module_allow_new_arb_cycle :  STD_LOGIC;
                signal CPU_jtag_debug_module_any_continuerequest :  STD_LOGIC;
                signal CPU_jtag_debug_module_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_arb_counter_enable :  STD_LOGIC;
                signal CPU_jtag_debug_module_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_arbitration_holdoff_internal :  STD_LOGIC;
                signal CPU_jtag_debug_module_beginbursttransfer_internal :  STD_LOGIC;
                signal CPU_jtag_debug_module_begins_xfer :  STD_LOGIC;
                signal CPU_jtag_debug_module_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal CPU_jtag_debug_module_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_end_xfer :  STD_LOGIC;
                signal CPU_jtag_debug_module_firsttransfer :  STD_LOGIC;
                signal CPU_jtag_debug_module_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_in_a_read_cycle :  STD_LOGIC;
                signal CPU_jtag_debug_module_in_a_write_cycle :  STD_LOGIC;
                signal CPU_jtag_debug_module_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_non_bursting_master_requests :  STD_LOGIC;
                signal CPU_jtag_debug_module_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_jtag_debug_module_slavearbiterlockenable :  STD_LOGIC;
                signal CPU_jtag_debug_module_slavearbiterlockenable2 :  STD_LOGIC;
                signal CPU_jtag_debug_module_waits_for_read :  STD_LOGIC;
                signal CPU_jtag_debug_module_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_data_master_requests_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_instruction_master_granted_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_instruction_master_requests_CPU_jtag_debug_module :  STD_LOGIC;
                signal internal_CPU_jtag_debug_module_reset_n :  STD_LOGIC;
                signal last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module :  STD_LOGIC;
                signal last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module :  STD_LOGIC;
                signal wait_for_CPU_jtag_debug_module_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT CPU_jtag_debug_module_end_xfer;
      end if;
    end if;

  end process;

  CPU_jtag_debug_module_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_CPU_data_master_qualified_request_CPU_jtag_debug_module OR internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module));
  --assign CPU_jtag_debug_module_readdata_from_sa = CPU_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  CPU_jtag_debug_module_readdata_from_sa <= CPU_jtag_debug_module_readdata;
  internal_CPU_data_master_requests_CPU_jtag_debug_module <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("100000001000000000000000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --CPU_jtag_debug_module_arb_share_counter set values, which is an e_mux
  CPU_jtag_debug_module_arb_share_set_values <= std_logic_vector'("01");
  --CPU_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  CPU_jtag_debug_module_non_bursting_master_requests <= ((internal_CPU_data_master_requests_CPU_jtag_debug_module OR internal_CPU_instruction_master_requests_CPU_jtag_debug_module) OR internal_CPU_data_master_requests_CPU_jtag_debug_module) OR internal_CPU_instruction_master_requests_CPU_jtag_debug_module;
  --CPU_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  CPU_jtag_debug_module_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(CPU_jtag_debug_module_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (CPU_jtag_debug_module_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(CPU_jtag_debug_module_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (CPU_jtag_debug_module_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --CPU_jtag_debug_module_allgrants all slave grants, which is an e_mux
  CPU_jtag_debug_module_allgrants <= ((or_reduce(CPU_jtag_debug_module_grant_vector) OR or_reduce(CPU_jtag_debug_module_grant_vector)) OR or_reduce(CPU_jtag_debug_module_grant_vector)) OR or_reduce(CPU_jtag_debug_module_grant_vector);
  --CPU_jtag_debug_module_end_xfer assignment, which is an e_assign
  CPU_jtag_debug_module_end_xfer <= NOT ((CPU_jtag_debug_module_waits_for_read OR CPU_jtag_debug_module_waits_for_write));
  --CPU_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  CPU_jtag_debug_module_arb_counter_enable <= ((CPU_jtag_debug_module_end_xfer AND CPU_jtag_debug_module_allgrants)) OR ((CPU_jtag_debug_module_end_xfer AND NOT CPU_jtag_debug_module_non_bursting_master_requests));
  --CPU_jtag_debug_module_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_jtag_debug_module_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(CPU_jtag_debug_module_arb_counter_enable) = '1' then 
        CPU_jtag_debug_module_arb_share_counter <= CPU_jtag_debug_module_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --CPU_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_jtag_debug_module_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((or_reduce(CPU_jtag_debug_module_master_qreq_vector) AND CPU_jtag_debug_module_end_xfer)) OR ((CPU_jtag_debug_module_end_xfer AND NOT CPU_jtag_debug_module_non_bursting_master_requests)))) = '1' then 
        CPU_jtag_debug_module_slavearbiterlockenable <= or_reduce(CPU_jtag_debug_module_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master CPU/jtag_debug_module arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= CPU_jtag_debug_module_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --CPU_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  CPU_jtag_debug_module_slavearbiterlockenable2 <= or_reduce(CPU_jtag_debug_module_arb_share_counter_next_value);
  --CPU/data_master CPU/jtag_debug_module arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= CPU_jtag_debug_module_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --CPU/instruction_master CPU/jtag_debug_module arbiterlock, which is an e_assign
  CPU_instruction_master_arbiterlock <= CPU_jtag_debug_module_slavearbiterlockenable AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master CPU/jtag_debug_module arbiterlock2, which is an e_assign
  CPU_instruction_master_arbiterlock2 <= CPU_jtag_debug_module_slavearbiterlockenable2 AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master granted CPU/jtag_debug_module last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_instruction_master_saved_grant_CPU_jtag_debug_module) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((CPU_jtag_debug_module_arbitration_holdoff_internal OR NOT internal_CPU_instruction_master_requests_CPU_jtag_debug_module))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module))))));
      end if;
    end if;

  end process;

  --CPU_instruction_master_continuerequest continued request, which is an e_mux
  CPU_instruction_master_continuerequest <= last_cycle_CPU_instruction_master_granted_slave_CPU_jtag_debug_module AND internal_CPU_instruction_master_requests_CPU_jtag_debug_module;
  --CPU_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  CPU_jtag_debug_module_any_continuerequest <= CPU_instruction_master_continuerequest OR CPU_data_master_continuerequest;
  internal_CPU_data_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_data_master_requests_CPU_jtag_debug_module AND NOT (CPU_instruction_master_arbiterlock);
  --CPU_jtag_debug_module_writedata mux, which is an e_mux
  CPU_jtag_debug_module_writedata <= CPU_data_master_writedata;
  --mux CPU_jtag_debug_module_debugaccess, which is an e_mux
  CPU_jtag_debug_module_debugaccess <= CPU_data_master_debugaccess;
  internal_CPU_instruction_master_requests_CPU_jtag_debug_module <= ((to_std_logic(((Std_Logic_Vector'(CPU_instruction_master_address_to_slave(23 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("100000001000000000000000")))) AND (CPU_instruction_master_read))) AND CPU_instruction_master_read;
  --CPU/data_master granted CPU/jtag_debug_module last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_data_master_saved_grant_CPU_jtag_debug_module) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((CPU_jtag_debug_module_arbitration_holdoff_internal OR NOT internal_CPU_data_master_requests_CPU_jtag_debug_module))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module))))));
      end if;
    end if;

  end process;

  --CPU_data_master_continuerequest continued request, which is an e_mux
  CPU_data_master_continuerequest <= last_cycle_CPU_data_master_granted_slave_CPU_jtag_debug_module AND internal_CPU_data_master_requests_CPU_jtag_debug_module;
  internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_instruction_master_requests_CPU_jtag_debug_module AND NOT ((((CPU_instruction_master_read AND ((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000")))) OR (CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register))))) OR CPU_data_master_arbiterlock));
  --local readdatavalid CPU_instruction_master_read_data_valid_CPU_jtag_debug_module, which is an e_mux
  CPU_instruction_master_read_data_valid_CPU_jtag_debug_module <= (internal_CPU_instruction_master_granted_CPU_jtag_debug_module AND CPU_instruction_master_read) AND NOT CPU_jtag_debug_module_waits_for_read;
  --allow new arb cycle for CPU/jtag_debug_module, which is an e_assign
  CPU_jtag_debug_module_allow_new_arb_cycle <= NOT CPU_data_master_arbiterlock AND NOT CPU_instruction_master_arbiterlock;
  --CPU/instruction_master assignment into master qualified-requests vector for CPU/jtag_debug_module, which is an e_assign
  CPU_jtag_debug_module_master_qreq_vector(0) <= internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module;
  --CPU/instruction_master grant CPU/jtag_debug_module, which is an e_assign
  internal_CPU_instruction_master_granted_CPU_jtag_debug_module <= CPU_jtag_debug_module_grant_vector(0);
  --CPU/instruction_master saved-grant CPU/jtag_debug_module, which is an e_assign
  CPU_instruction_master_saved_grant_CPU_jtag_debug_module <= CPU_jtag_debug_module_arb_winner(0) AND internal_CPU_instruction_master_requests_CPU_jtag_debug_module;
  --CPU/data_master assignment into master qualified-requests vector for CPU/jtag_debug_module, which is an e_assign
  CPU_jtag_debug_module_master_qreq_vector(1) <= internal_CPU_data_master_qualified_request_CPU_jtag_debug_module;
  --CPU/data_master grant CPU/jtag_debug_module, which is an e_assign
  internal_CPU_data_master_granted_CPU_jtag_debug_module <= CPU_jtag_debug_module_grant_vector(1);
  --CPU/data_master saved-grant CPU/jtag_debug_module, which is an e_assign
  CPU_data_master_saved_grant_CPU_jtag_debug_module <= CPU_jtag_debug_module_arb_winner(1) AND internal_CPU_data_master_requests_CPU_jtag_debug_module;
  --CPU/jtag_debug_module chosen-master double-vector, which is an e_assign
  CPU_jtag_debug_module_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((CPU_jtag_debug_module_master_qreq_vector & CPU_jtag_debug_module_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT CPU_jtag_debug_module_master_qreq_vector & NOT CPU_jtag_debug_module_master_qreq_vector))) + (std_logic_vector'("000") & (CPU_jtag_debug_module_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  CPU_jtag_debug_module_arb_winner <= A_WE_StdLogicVector((std_logic'(((CPU_jtag_debug_module_allow_new_arb_cycle AND or_reduce(CPU_jtag_debug_module_grant_vector)))) = '1'), CPU_jtag_debug_module_grant_vector, CPU_jtag_debug_module_saved_chosen_master_vector);
  --saved CPU_jtag_debug_module_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_jtag_debug_module_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(CPU_jtag_debug_module_allow_new_arb_cycle) = '1' then 
        CPU_jtag_debug_module_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(CPU_jtag_debug_module_grant_vector)) = '1'), CPU_jtag_debug_module_grant_vector, CPU_jtag_debug_module_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  CPU_jtag_debug_module_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((CPU_jtag_debug_module_chosen_master_double_vector(1) OR CPU_jtag_debug_module_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((CPU_jtag_debug_module_chosen_master_double_vector(0) OR CPU_jtag_debug_module_chosen_master_double_vector(2)))));
  --CPU/jtag_debug_module chosen master rotated left, which is an e_assign
  CPU_jtag_debug_module_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(CPU_jtag_debug_module_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(CPU_jtag_debug_module_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --CPU/jtag_debug_module's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_jtag_debug_module_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(CPU_jtag_debug_module_grant_vector)) = '1' then 
        CPU_jtag_debug_module_arb_addend <= A_WE_StdLogicVector((std_logic'(CPU_jtag_debug_module_end_xfer) = '1'), CPU_jtag_debug_module_chosen_master_rot_left, CPU_jtag_debug_module_grant_vector);
      end if;
    end if;

  end process;

  CPU_jtag_debug_module_begintransfer <= CPU_jtag_debug_module_begins_xfer;
  --assign lhs ~CPU_jtag_debug_module_reset of type reset_n to CPU_jtag_debug_module_reset_n, which is an e_assign
  CPU_jtag_debug_module_reset <= NOT internal_CPU_jtag_debug_module_reset_n;
  --CPU_jtag_debug_module_reset_n assignment, which is an e_assign
  internal_CPU_jtag_debug_module_reset_n <= reset_n;
  --assign CPU_jtag_debug_module_resetrequest_from_sa = CPU_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  CPU_jtag_debug_module_resetrequest_from_sa <= CPU_jtag_debug_module_resetrequest;
  CPU_jtag_debug_module_chipselect <= internal_CPU_data_master_granted_CPU_jtag_debug_module OR internal_CPU_instruction_master_granted_CPU_jtag_debug_module;
  --CPU_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  CPU_jtag_debug_module_firsttransfer <= NOT ((CPU_jtag_debug_module_slavearbiterlockenable AND CPU_jtag_debug_module_any_continuerequest));
  --CPU_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  CPU_jtag_debug_module_beginbursttransfer_internal <= CPU_jtag_debug_module_begins_xfer AND CPU_jtag_debug_module_firsttransfer;
  --CPU_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  CPU_jtag_debug_module_arbitration_holdoff_internal <= CPU_jtag_debug_module_begins_xfer AND CPU_jtag_debug_module_firsttransfer;
  --CPU_jtag_debug_module_write assignment, which is an e_mux
  CPU_jtag_debug_module_write <= internal_CPU_data_master_granted_CPU_jtag_debug_module AND CPU_data_master_write;
  --CPU_jtag_debug_module_address mux, which is an e_mux
  CPU_jtag_debug_module_address <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_CPU_jtag_debug_module)) = '1'), (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010"))), (A_SRL(CPU_instruction_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")))), 9);
  --d1_CPU_jtag_debug_module_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_CPU_jtag_debug_module_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_CPU_jtag_debug_module_end_xfer <= CPU_jtag_debug_module_end_xfer;
      end if;
    end if;

  end process;

  --CPU_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  CPU_jtag_debug_module_waits_for_read <= CPU_jtag_debug_module_in_a_read_cycle AND CPU_jtag_debug_module_begins_xfer;
  --CPU_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  CPU_jtag_debug_module_in_a_read_cycle <= ((internal_CPU_data_master_granted_CPU_jtag_debug_module AND CPU_data_master_read)) OR ((internal_CPU_instruction_master_granted_CPU_jtag_debug_module AND CPU_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= CPU_jtag_debug_module_in_a_read_cycle;
  --CPU_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  CPU_jtag_debug_module_waits_for_write <= CPU_jtag_debug_module_in_a_write_cycle AND CPU_jtag_debug_module_begins_xfer;
  --CPU_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  CPU_jtag_debug_module_in_a_write_cycle <= internal_CPU_data_master_granted_CPU_jtag_debug_module AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= CPU_jtag_debug_module_in_a_write_cycle;
  wait_for_CPU_jtag_debug_module_counter <= std_logic'('0');
  --CPU_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  CPU_jtag_debug_module_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_CPU_jtag_debug_module)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (CPU_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --vhdl renameroo for output signals
  CPU_data_master_granted_CPU_jtag_debug_module <= internal_CPU_data_master_granted_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_data_master_qualified_request_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_data_master_requests_CPU_jtag_debug_module <= internal_CPU_data_master_requests_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_instruction_master_granted_CPU_jtag_debug_module <= internal_CPU_instruction_master_granted_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_instruction_master_qualified_request_CPU_jtag_debug_module <= internal_CPU_instruction_master_qualified_request_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_instruction_master_requests_CPU_jtag_debug_module <= internal_CPU_instruction_master_requests_CPU_jtag_debug_module;
  --vhdl renameroo for output signals
  CPU_jtag_debug_module_reset_n <= internal_CPU_jtag_debug_module_reset_n;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line2 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_data_master_granted_CPU_jtag_debug_module))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_instruction_master_granted_CPU_jtag_debug_module))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line2, now);
          write(write_line2, string'(": "));
          write(write_line2, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line2.all);
          deallocate (write_line2);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line3 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_data_master_saved_grant_CPU_jtag_debug_module))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_saved_grant_CPU_jtag_debug_module))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line3, now);
          write(write_line3, string'(": "));
          write(write_line3, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line3.all);
          deallocate (write_line3);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_data_master_arbitrator is 
        port (
              -- inputs:
                 signal AVALON_avalon_slave_irq_from_sa : IN STD_LOGIC;
                 signal AVALON_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal AVALON_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
                 signal CPU_data_master_address : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable_SDRAM_s1 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_data_master_debugaccess : IN STD_LOGIC;
                 signal CPU_data_master_granted_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_data_master_granted_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_data_master_granted_IRDA_s1 : IN STD_LOGIC;
                 signal CPU_data_master_granted_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                 signal CPU_data_master_granted_KEYS_s1 : IN STD_LOGIC;
                 signal CPU_data_master_granted_LCD_control_slave : IN STD_LOGIC;
                 signal CPU_data_master_granted_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_data_master_granted_SWITCHES_s1 : IN STD_LOGIC;
                 signal CPU_data_master_granted_TIMER0_s1 : IN STD_LOGIC;
                 signal CPU_data_master_granted_clock_0_in : IN STD_LOGIC;
                 signal CPU_data_master_granted_clock_1_in : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_IRDA_s1 : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_KEYS_s1 : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_LCD_control_slave : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_SWITCHES_s1 : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_TIMER0_s1 : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_clock_0_in : IN STD_LOGIC;
                 signal CPU_data_master_qualified_request_clock_1_in : IN STD_LOGIC;
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_IRDA_s1 : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_KEYS_s1 : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_LCD_control_slave : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SWITCHES_s1 : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_TIMER0_s1 : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_clock_0_in : IN STD_LOGIC;
                 signal CPU_data_master_read_data_valid_clock_1_in : IN STD_LOGIC;
                 signal CPU_data_master_requests_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_data_master_requests_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_data_master_requests_IRDA_s1 : IN STD_LOGIC;
                 signal CPU_data_master_requests_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                 signal CPU_data_master_requests_KEYS_s1 : IN STD_LOGIC;
                 signal CPU_data_master_requests_LCD_control_slave : IN STD_LOGIC;
                 signal CPU_data_master_requests_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_data_master_requests_SWITCHES_s1 : IN STD_LOGIC;
                 signal CPU_data_master_requests_TIMER0_s1 : IN STD_LOGIC;
                 signal CPU_data_master_requests_clock_0_in : IN STD_LOGIC;
                 signal CPU_data_master_requests_clock_1_in : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal IRDA_s1_irq_from_sa : IN STD_LOGIC;
                 signal IRDA_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal JTAG_avalon_jtag_slave_irq_from_sa : IN STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal JTAG_avalon_jtag_slave_waitrequest_from_sa : IN STD_LOGIC;
                 signal KEYS_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal LCD_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal LCD_control_slave_wait_counter_eq_0 : IN STD_LOGIC;
                 signal LCD_control_slave_wait_counter_eq_1 : IN STD_LOGIC;
                 signal SDRAM_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal SDRAM_s1_waitrequest_from_sa : IN STD_LOGIC;
                 signal SWITCHES_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal TIMER0_s1_irq_from_sa : IN STD_LOGIC;
                 signal TIMER0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_0_in_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clock_0_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal clock_1_in_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clock_1_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal d1_AVALON_avalon_slave_end_xfer : IN STD_LOGIC;
                 signal d1_CPU_jtag_debug_module_end_xfer : IN STD_LOGIC;
                 signal d1_IRDA_s1_end_xfer : IN STD_LOGIC;
                 signal d1_JTAG_avalon_jtag_slave_end_xfer : IN STD_LOGIC;
                 signal d1_KEYS_s1_end_xfer : IN STD_LOGIC;
                 signal d1_LCD_control_slave_end_xfer : IN STD_LOGIC;
                 signal d1_SDRAM_s1_end_xfer : IN STD_LOGIC;
                 signal d1_SWITCHES_s1_end_xfer : IN STD_LOGIC;
                 signal d1_TIMER0_s1_end_xfer : IN STD_LOGIC;
                 signal d1_clock_0_in_end_xfer : IN STD_LOGIC;
                 signal d1_clock_1_in_end_xfer : IN STD_LOGIC;
                 signal registered_CPU_data_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_address_to_slave : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_data_master_dbs_write_16 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal CPU_data_master_irq : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_data_master_no_byte_enables_and_last_term : OUT STD_LOGIC;
                 signal CPU_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_data_master_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of CPU_data_master_arbitrator : entity is FALSE;
end entity CPU_data_master_arbitrator;


architecture europa of CPU_data_master_arbitrator is
                signal CPU_data_master_dbs_increment :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_data_master_run :  STD_LOGIC;
                signal dbs_16_reg_segment_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dbs_count_enable :  STD_LOGIC;
                signal dbs_counter_overflow :  STD_LOGIC;
                signal internal_CPU_data_master_address_to_slave :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal internal_CPU_data_master_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_CPU_data_master_no_byte_enables_and_last_term :  STD_LOGIC;
                signal internal_CPU_data_master_waitrequest :  STD_LOGIC;
                signal last_dbs_term_and_run :  STD_LOGIC;
                signal next_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal p1_dbs_16_reg_segment_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal p1_registered_CPU_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal pre_dbs_count_enable :  STD_LOGIC;
                signal r_0 :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;
                signal r_2 :  STD_LOGIC;
                signal registered_CPU_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --r_0 master_run cascaded wait assignment, which is an e_assign
  r_0 <= Vector_To_Std_Logic((((((((((((((((((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((CPU_data_master_qualified_request_AVALON_avalon_slave OR registered_CPU_data_master_read_data_valid_AVALON_avalon_slave) OR NOT CPU_data_master_requests_AVALON_avalon_slave)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_granted_AVALON_avalon_slave OR NOT CPU_data_master_qualified_request_AVALON_avalon_slave)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT CPU_data_master_qualified_request_AVALON_avalon_slave OR NOT CPU_data_master_read) OR ((registered_CPU_data_master_read_data_valid_AVALON_avalon_slave AND CPU_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_AVALON_avalon_slave OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT AVALON_avalon_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_CPU_jtag_debug_module OR NOT CPU_data_master_requests_CPU_jtag_debug_module)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_granted_CPU_jtag_debug_module OR NOT CPU_data_master_qualified_request_CPU_jtag_debug_module)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_CPU_jtag_debug_module OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_CPU_jtag_debug_module OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_IRDA_s1 OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_IRDA_s1 OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_JTAG_avalon_jtag_slave OR NOT CPU_data_master_requests_JTAG_avalon_jtag_slave)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_JTAG_avalon_jtag_slave OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT JTAG_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_JTAG_avalon_jtag_slave OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT JTAG_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_KEYS_s1 OR NOT CPU_data_master_requests_KEYS_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_KEYS_s1 OR NOT CPU_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_read)))))))));
  --cascaded wait assignment, which is an e_assign
  CPU_data_master_run <= (r_0 AND r_1) AND r_2;
  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((((((((((((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_KEYS_s1 OR NOT CPU_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_write))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_LCD_control_slave OR NOT CPU_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(LCD_control_slave_wait_counter_eq_1)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_LCD_control_slave OR NOT CPU_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(LCD_control_slave_wait_counter_eq_1)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((((CPU_data_master_qualified_request_SDRAM_s1 OR ((CPU_data_master_read_data_valid_SDRAM_s1 AND internal_CPU_data_master_dbs_address(1)))) OR (((CPU_data_master_write AND NOT(or_reduce(CPU_data_master_byteenable_SDRAM_s1))) AND internal_CPU_data_master_dbs_address(1)))) OR NOT CPU_data_master_requests_SDRAM_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_granted_SDRAM_s1 OR NOT CPU_data_master_qualified_request_SDRAM_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT CPU_data_master_qualified_request_SDRAM_s1 OR NOT CPU_data_master_read) OR (((CPU_data_master_read_data_valid_SDRAM_s1 AND (internal_CPU_data_master_dbs_address(1))) AND CPU_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_SDRAM_s1 OR NOT CPU_data_master_write)))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT SDRAM_s1_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_CPU_data_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_SWITCHES_s1 OR NOT CPU_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_SWITCHES_s1 OR NOT CPU_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_TIMER0_s1 OR NOT CPU_data_master_requests_TIMER0_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_TIMER0_s1 OR NOT CPU_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_TIMER0_s1 OR NOT CPU_data_master_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_clock_0_in OR NOT CPU_data_master_requests_clock_0_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_clock_0_in OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_0_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_clock_0_in OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_0_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))));
  --r_2 master_run cascaded wait assignment, which is an e_assign
  r_2 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_qualified_request_clock_1_in OR NOT CPU_data_master_requests_clock_1_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_clock_1_in OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_1_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_data_master_qualified_request_clock_1_in OR NOT ((CPU_data_master_read OR CPU_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_1_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_read OR CPU_data_master_write)))))))))));
  --optimize select-logic by passing only those address bits which matter.
  internal_CPU_data_master_address_to_slave <= CPU_data_master_address(23 DOWNTO 0);
  --CPU/data_master readdata mux, which is an e_mux
  CPU_data_master_readdata <= (((((((((((A_REP(NOT CPU_data_master_requests_AVALON_avalon_slave, 32) OR AVALON_avalon_slave_readdata_from_sa)) AND ((A_REP(NOT CPU_data_master_requests_CPU_jtag_debug_module, 32) OR CPU_jtag_debug_module_readdata_from_sa))) AND ((A_REP(NOT CPU_data_master_requests_IRDA_s1, 32) OR (std_logic_vector'("0000000000000000") & (IRDA_s1_readdata_from_sa))))) AND ((A_REP(NOT CPU_data_master_requests_JTAG_avalon_jtag_slave, 32) OR registered_CPU_data_master_readdata))) AND ((A_REP(NOT CPU_data_master_requests_KEYS_s1, 32) OR (std_logic_vector'("0000000000000000000000000000") & (KEYS_s1_readdata_from_sa))))) AND ((A_REP(NOT CPU_data_master_requests_LCD_control_slave, 32) OR (std_logic_vector'("000000000000000000000000") & (LCD_control_slave_readdata_from_sa))))) AND ((A_REP(NOT CPU_data_master_requests_SDRAM_s1, 32) OR registered_CPU_data_master_readdata))) AND ((A_REP(NOT CPU_data_master_requests_SWITCHES_s1, 32) OR (std_logic_vector'("00000000000000") & (SWITCHES_s1_readdata_from_sa))))) AND ((A_REP(NOT CPU_data_master_requests_TIMER0_s1, 32) OR (std_logic_vector'("0000000000000000") & (TIMER0_s1_readdata_from_sa))))) AND ((A_REP(NOT CPU_data_master_requests_clock_0_in, 32) OR registered_CPU_data_master_readdata))) AND ((A_REP(NOT CPU_data_master_requests_clock_1_in, 32) OR registered_CPU_data_master_readdata));
  --actual waitrequest port, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_CPU_data_master_waitrequest <= Vector_To_Std_Logic(NOT std_logic_vector'("00000000000000000000000000000000"));
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        internal_CPU_data_master_waitrequest <= Vector_To_Std_Logic(NOT (A_WE_StdLogicVector((std_logic'((NOT ((CPU_data_master_read OR CPU_data_master_write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_data_master_run AND internal_CPU_data_master_waitrequest))))))));
      end if;
    end if;

  end process;

  --irq assign, which is an e_assign
  CPU_data_master_irq <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(AVALON_avalon_slave_irq_from_sa) & A_ToStdLogicVector(IRDA_s1_irq_from_sa) & A_ToStdLogicVector(JTAG_avalon_jtag_slave_irq_from_sa) & A_ToStdLogicVector(TIMER0_s1_irq_from_sa));
  --unpredictable registered wait state incoming data, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      registered_CPU_data_master_readdata <= std_logic_vector'("00000000000000000000000000000000");
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        registered_CPU_data_master_readdata <= p1_registered_CPU_data_master_readdata;
      end if;
    end if;

  end process;

  --registered readdata mux, which is an e_mux
  p1_registered_CPU_data_master_readdata <= ((((A_REP(NOT CPU_data_master_requests_JTAG_avalon_jtag_slave, 32) OR JTAG_avalon_jtag_slave_readdata_from_sa)) AND ((A_REP(NOT CPU_data_master_requests_SDRAM_s1, 32) OR Std_Logic_Vector'(SDRAM_s1_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)))) AND ((A_REP(NOT CPU_data_master_requests_clock_0_in, 32) OR clock_0_in_readdata_from_sa))) AND ((A_REP(NOT CPU_data_master_requests_clock_1_in, 32) OR (std_logic_vector'("0000000000000000") & (clock_1_in_readdata_from_sa))));
  --no_byte_enables_and_last_term, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_CPU_data_master_no_byte_enables_and_last_term <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        internal_CPU_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
      end if;
    end if;

  end process;

  --compute the last dbs term, which is an e_mux
  last_dbs_term_and_run <= (to_std_logic(((internal_CPU_data_master_dbs_address = std_logic_vector'("10")))) AND CPU_data_master_write) AND NOT(or_reduce(CPU_data_master_byteenable_SDRAM_s1));
  --pre dbs count enable, which is an e_mux
  pre_dbs_count_enable <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((((((NOT internal_CPU_data_master_no_byte_enables_and_last_term) AND CPU_data_master_requests_SDRAM_s1) AND CPU_data_master_write) AND NOT(or_reduce(CPU_data_master_byteenable_SDRAM_s1)))) OR CPU_data_master_read_data_valid_SDRAM_s1)))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((CPU_data_master_granted_SDRAM_s1 AND CPU_data_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT SDRAM_s1_waitrequest_from_sa)))))));
  --input to dbs-16 stored 0, which is an e_mux
  p1_dbs_16_reg_segment_0 <= SDRAM_s1_readdata_from_sa;
  --dbs register for dbs-16 segment 0, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dbs_16_reg_segment_0 <= std_logic_vector'("0000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'((dbs_count_enable AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_CPU_data_master_dbs_address(1))))) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then 
        dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
      end if;
    end if;

  end process;

  --mux write dbs 1, which is an e_mux
  CPU_data_master_dbs_write_16 <= A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_dbs_address(1))) = '1'), CPU_data_master_writedata(31 DOWNTO 16), CPU_data_master_writedata(15 DOWNTO 0));
  --dbs count increment, which is an e_mux
  CPU_data_master_dbs_increment <= A_EXT (A_WE_StdLogicVector((std_logic'((CPU_data_master_requests_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000000")), 2);
  --dbs counter overflow, which is an e_assign
  dbs_counter_overflow <= internal_CPU_data_master_dbs_address(1) AND NOT((next_dbs_address(1)));
  --next master address, which is an e_assign
  next_dbs_address <= A_EXT (((std_logic_vector'("0") & (internal_CPU_data_master_dbs_address)) + (std_logic_vector'("0") & (CPU_data_master_dbs_increment))), 2);
  --dbs count enable, which is an e_mux
  dbs_count_enable <= pre_dbs_count_enable AND (NOT ((CPU_data_master_requests_SDRAM_s1 AND NOT internal_CPU_data_master_waitrequest)));
  --dbs counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_CPU_data_master_dbs_address <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(dbs_count_enable) = '1' then 
        internal_CPU_data_master_dbs_address <= next_dbs_address;
      end if;
    end if;

  end process;

  --vhdl renameroo for output signals
  CPU_data_master_address_to_slave <= internal_CPU_data_master_address_to_slave;
  --vhdl renameroo for output signals
  CPU_data_master_dbs_address <= internal_CPU_data_master_dbs_address;
  --vhdl renameroo for output signals
  CPU_data_master_no_byte_enables_and_last_term <= internal_CPU_data_master_no_byte_enables_and_last_term;
  --vhdl renameroo for output signals
  CPU_data_master_waitrequest <= internal_CPU_data_master_waitrequest;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity CPU_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal AVALON_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal AVALON_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
                 signal CPU_instruction_master_address : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_instruction_master_granted_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_instruction_master_granted_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_instruction_master_granted_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_instruction_master_read : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                 signal CPU_instruction_master_requests_AVALON_avalon_slave : IN STD_LOGIC;
                 signal CPU_instruction_master_requests_CPU_jtag_debug_module : IN STD_LOGIC;
                 signal CPU_instruction_master_requests_SDRAM_s1 : IN STD_LOGIC;
                 signal CPU_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal SDRAM_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal SDRAM_s1_waitrequest_from_sa : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal d1_AVALON_avalon_slave_end_xfer : IN STD_LOGIC;
                 signal d1_CPU_jtag_debug_module_end_xfer : IN STD_LOGIC;
                 signal d1_SDRAM_s1_end_xfer : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_instruction_master_address_to_slave : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_instruction_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_instruction_master_latency_counter : OUT STD_LOGIC;
                 signal CPU_instruction_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal CPU_instruction_master_readdatavalid : OUT STD_LOGIC;
                 signal CPU_instruction_master_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of CPU_instruction_master_arbitrator : entity is FALSE;
end entity CPU_instruction_master_arbitrator;


architecture europa of CPU_instruction_master_arbitrator is
                signal CPU_instruction_master_address_last_time :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal CPU_instruction_master_dbs_increment :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_instruction_master_dbs_rdv_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_instruction_master_dbs_rdv_counter_inc :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_instruction_master_is_granted_some_slave :  STD_LOGIC;
                signal CPU_instruction_master_next_dbs_rdv_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_instruction_master_read_but_no_slave_selected :  STD_LOGIC;
                signal CPU_instruction_master_read_last_time :  STD_LOGIC;
                signal CPU_instruction_master_run :  STD_LOGIC;
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal dbs_count_enable :  STD_LOGIC;
                signal dbs_counter_overflow :  STD_LOGIC;
                signal dbs_latent_16_reg_segment_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dbs_rdv_count_enable :  STD_LOGIC;
                signal dbs_rdv_counter_overflow :  STD_LOGIC;
                signal internal_CPU_instruction_master_address_to_slave :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal internal_CPU_instruction_master_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_CPU_instruction_master_latency_counter :  STD_LOGIC;
                signal internal_CPU_instruction_master_waitrequest :  STD_LOGIC;
                signal latency_load_value :  STD_LOGIC;
                signal next_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal p1_CPU_instruction_master_latency_counter :  STD_LOGIC;
                signal p1_dbs_latent_16_reg_segment_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal pre_dbs_count_enable :  STD_LOGIC;
                signal pre_flush_CPU_instruction_master_readdatavalid :  STD_LOGIC;
                signal r_0 :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_0 master_run cascaded wait assignment, which is an e_assign
  r_0 <= Vector_To_Std_Logic((((((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_qualified_request_AVALON_avalon_slave OR NOT CPU_instruction_master_requests_AVALON_avalon_slave)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_granted_AVALON_avalon_slave OR NOT CPU_instruction_master_qualified_request_AVALON_avalon_slave)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_instruction_master_qualified_request_AVALON_avalon_slave OR NOT CPU_instruction_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT AVALON_avalon_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_read)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_qualified_request_CPU_jtag_debug_module OR NOT CPU_instruction_master_requests_CPU_jtag_debug_module)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_granted_CPU_jtag_debug_module OR NOT CPU_instruction_master_qualified_request_CPU_jtag_debug_module)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_instruction_master_qualified_request_CPU_jtag_debug_module OR NOT (CPU_instruction_master_read))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_CPU_jtag_debug_module_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((CPU_instruction_master_read))))))))));
  --cascaded wait assignment, which is an e_assign
  CPU_instruction_master_run <= r_0 AND r_1;
  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_qualified_request_SDRAM_s1 OR NOT CPU_instruction_master_requests_SDRAM_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((CPU_instruction_master_granted_SDRAM_s1 OR NOT CPU_instruction_master_qualified_request_SDRAM_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT CPU_instruction_master_qualified_request_SDRAM_s1 OR NOT CPU_instruction_master_read)))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT SDRAM_s1_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_CPU_instruction_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_read)))))))));
  --optimize select-logic by passing only those address bits which matter.
  internal_CPU_instruction_master_address_to_slave <= CPU_instruction_master_address(23 DOWNTO 0);
  --CPU_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_instruction_master_read_but_no_slave_selected <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        CPU_instruction_master_read_but_no_slave_selected <= (CPU_instruction_master_read AND CPU_instruction_master_run) AND NOT CPU_instruction_master_is_granted_some_slave;
      end if;
    end if;

  end process;

  --some slave is getting selected, which is an e_mux
  CPU_instruction_master_is_granted_some_slave <= (CPU_instruction_master_granted_AVALON_avalon_slave OR CPU_instruction_master_granted_CPU_jtag_debug_module) OR CPU_instruction_master_granted_SDRAM_s1;
  --latent slave read data valids which may be flushed, which is an e_mux
  pre_flush_CPU_instruction_master_readdatavalid <= CPU_instruction_master_read_data_valid_AVALON_avalon_slave OR ((CPU_instruction_master_read_data_valid_SDRAM_s1 AND dbs_rdv_counter_overflow));
  --latent slave read data valid which is not flushed, which is an e_mux
  CPU_instruction_master_readdatavalid <= (((((CPU_instruction_master_read_but_no_slave_selected OR pre_flush_CPU_instruction_master_readdatavalid) OR CPU_instruction_master_read_but_no_slave_selected) OR pre_flush_CPU_instruction_master_readdatavalid) OR CPU_instruction_master_read_data_valid_CPU_jtag_debug_module) OR CPU_instruction_master_read_but_no_slave_selected) OR pre_flush_CPU_instruction_master_readdatavalid;
  --CPU/instruction_master readdata mux, which is an e_mux
  CPU_instruction_master_readdata <= (((A_REP(NOT CPU_instruction_master_read_data_valid_AVALON_avalon_slave, 32) OR AVALON_avalon_slave_readdata_from_sa)) AND ((A_REP(NOT CPU_instruction_master_qualified_request_CPU_jtag_debug_module, 32) OR CPU_jtag_debug_module_readdata_from_sa))) AND ((A_REP(NOT CPU_instruction_master_read_data_valid_SDRAM_s1, 32) OR Std_Logic_Vector'(SDRAM_s1_readdata_from_sa(15 DOWNTO 0) & dbs_latent_16_reg_segment_0)));
  --actual waitrequest port, which is an e_assign
  internal_CPU_instruction_master_waitrequest <= NOT CPU_instruction_master_run;
  --latent max counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_CPU_instruction_master_latency_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        internal_CPU_instruction_master_latency_counter <= p1_CPU_instruction_master_latency_counter;
      end if;
    end if;

  end process;

  --latency counter load mux, which is an e_mux
  p1_CPU_instruction_master_latency_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((CPU_instruction_master_run AND CPU_instruction_master_read))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(latency_load_value))), A_WE_StdLogicVector((std_logic'((internal_CPU_instruction_master_latency_counter)) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_CPU_instruction_master_latency_counter))) - std_logic_vector'("000000000000000000000000000000001")), std_logic_vector'("000000000000000000000000000000000"))));
  --read latency load values, which is an e_mux
  latency_load_value <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_requests_AVALON_avalon_slave))) AND std_logic_vector'("00000000000000000000000000000001")));
  --input to latent dbs-16 stored 0, which is an e_mux
  p1_dbs_latent_16_reg_segment_0 <= SDRAM_s1_readdata_from_sa;
  --dbs register for latent dbs-16 segment 0, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dbs_latent_16_reg_segment_0 <= std_logic_vector'("0000000000000000");
    elsif clk'event and clk = '1' then
      if std_logic'((dbs_rdv_count_enable AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((CPU_instruction_master_dbs_rdv_counter(1))))) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then 
        dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
      end if;
    end if;

  end process;

  --dbs count increment, which is an e_mux
  CPU_instruction_master_dbs_increment <= A_EXT (A_WE_StdLogicVector((std_logic'((CPU_instruction_master_requests_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000000")), 2);
  --dbs counter overflow, which is an e_assign
  dbs_counter_overflow <= internal_CPU_instruction_master_dbs_address(1) AND NOT((next_dbs_address(1)));
  --next master address, which is an e_assign
  next_dbs_address <= A_EXT (((std_logic_vector'("0") & (internal_CPU_instruction_master_dbs_address)) + (std_logic_vector'("0") & (CPU_instruction_master_dbs_increment))), 2);
  --dbs count enable, which is an e_mux
  dbs_count_enable <= pre_dbs_count_enable;
  --dbs counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_CPU_instruction_master_dbs_address <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(dbs_count_enable) = '1' then 
        internal_CPU_instruction_master_dbs_address <= next_dbs_address;
      end if;
    end if;

  end process;

  --p1 dbs rdv counter, which is an e_assign
  CPU_instruction_master_next_dbs_rdv_counter <= A_EXT (((std_logic_vector'("0") & (CPU_instruction_master_dbs_rdv_counter)) + (std_logic_vector'("0") & (CPU_instruction_master_dbs_rdv_counter_inc))), 2);
  --CPU_instruction_master_rdv_inc_mux, which is an e_mux
  CPU_instruction_master_dbs_rdv_counter_inc <= std_logic_vector'("10");
  --master any slave rdv, which is an e_mux
  dbs_rdv_count_enable <= CPU_instruction_master_read_data_valid_SDRAM_s1;
  --dbs rdv counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      CPU_instruction_master_dbs_rdv_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(dbs_rdv_count_enable) = '1' then 
        CPU_instruction_master_dbs_rdv_counter <= CPU_instruction_master_next_dbs_rdv_counter;
      end if;
    end if;

  end process;

  --dbs rdv counter overflow, which is an e_assign
  dbs_rdv_counter_overflow <= CPU_instruction_master_dbs_rdv_counter(1) AND NOT CPU_instruction_master_next_dbs_rdv_counter(1);
  --pre dbs count enable, which is an e_mux
  pre_dbs_count_enable <= Vector_To_Std_Logic(((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((CPU_instruction_master_granted_SDRAM_s1 AND CPU_instruction_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT SDRAM_s1_waitrequest_from_sa)))));
  --vhdl renameroo for output signals
  CPU_instruction_master_address_to_slave <= internal_CPU_instruction_master_address_to_slave;
  --vhdl renameroo for output signals
  CPU_instruction_master_dbs_address <= internal_CPU_instruction_master_dbs_address;
  --vhdl renameroo for output signals
  CPU_instruction_master_latency_counter <= internal_CPU_instruction_master_latency_counter;
  --vhdl renameroo for output signals
  CPU_instruction_master_waitrequest <= internal_CPU_instruction_master_waitrequest;
--synthesis translate_off
    --CPU_instruction_master_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        CPU_instruction_master_address_last_time <= std_logic_vector'("000000000000000000000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          CPU_instruction_master_address_last_time <= CPU_instruction_master_address;
        end if;
      end if;

    end process;

    --CPU/instruction_master waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_CPU_instruction_master_waitrequest AND (CPU_instruction_master_read);
        end if;
      end if;

    end process;

    --CPU_instruction_master_address matches last port_name, which is an e_process
    process (CPU_instruction_master_address, CPU_instruction_master_address_last_time, active_and_waiting_last_time)
    VARIABLE write_line4 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((CPU_instruction_master_address /= CPU_instruction_master_address_last_time))))) = '1' then 
          write(write_line4, now);
          write(write_line4, string'(": "));
          write(write_line4, string'("CPU_instruction_master_address did not heed wait!!!"));
          write(output, write_line4.all);
          deallocate (write_line4);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --CPU_instruction_master_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        CPU_instruction_master_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          CPU_instruction_master_read_last_time <= CPU_instruction_master_read;
        end if;
      end if;

    end process;

    --CPU_instruction_master_read matches last port_name, which is an e_process
    process (CPU_instruction_master_read, CPU_instruction_master_read_last_time, active_and_waiting_last_time)
    VARIABLE write_line5 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(CPU_instruction_master_read) /= std_logic'(CPU_instruction_master_read_last_time)))))) = '1' then 
          write(write_line5, now);
          write(write_line5, string'(": "));
          write(write_line5, string'("CPU_instruction_master_read did not heed wait!!!"));
          write(output, write_line5.all);
          deallocate (write_line5);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity IRDA_s1_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal IRDA_s1_dataavailable : IN STD_LOGIC;
                 signal IRDA_s1_irq : IN STD_LOGIC;
                 signal IRDA_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal IRDA_s1_readyfordata : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_IRDA_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_IRDA_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_IRDA_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_requests_IRDA_s1 : OUT STD_LOGIC;
                 signal IRDA_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal IRDA_s1_begintransfer : OUT STD_LOGIC;
                 signal IRDA_s1_chipselect : OUT STD_LOGIC;
                 signal IRDA_s1_dataavailable_from_sa : OUT STD_LOGIC;
                 signal IRDA_s1_irq_from_sa : OUT STD_LOGIC;
                 signal IRDA_s1_read_n : OUT STD_LOGIC;
                 signal IRDA_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal IRDA_s1_readyfordata_from_sa : OUT STD_LOGIC;
                 signal IRDA_s1_reset_n : OUT STD_LOGIC;
                 signal IRDA_s1_write_n : OUT STD_LOGIC;
                 signal IRDA_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_IRDA_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of IRDA_s1_arbitrator : entity is FALSE;
end entity IRDA_s1_arbitrator;


architecture europa of IRDA_s1_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_IRDA_s1 :  STD_LOGIC;
                signal IRDA_s1_allgrants :  STD_LOGIC;
                signal IRDA_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal IRDA_s1_any_continuerequest :  STD_LOGIC;
                signal IRDA_s1_arb_counter_enable :  STD_LOGIC;
                signal IRDA_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal IRDA_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal IRDA_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal IRDA_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal IRDA_s1_begins_xfer :  STD_LOGIC;
                signal IRDA_s1_end_xfer :  STD_LOGIC;
                signal IRDA_s1_firsttransfer :  STD_LOGIC;
                signal IRDA_s1_grant_vector :  STD_LOGIC;
                signal IRDA_s1_in_a_read_cycle :  STD_LOGIC;
                signal IRDA_s1_in_a_write_cycle :  STD_LOGIC;
                signal IRDA_s1_master_qreq_vector :  STD_LOGIC;
                signal IRDA_s1_non_bursting_master_requests :  STD_LOGIC;
                signal IRDA_s1_slavearbiterlockenable :  STD_LOGIC;
                signal IRDA_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal IRDA_s1_waits_for_read :  STD_LOGIC;
                signal IRDA_s1_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_IRDA_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_IRDA_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_requests_IRDA_s1 :  STD_LOGIC;
                signal wait_for_IRDA_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT IRDA_s1_end_xfer;
      end if;
    end if;

  end process;

  IRDA_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_IRDA_s1);
  --assign IRDA_s1_readdata_from_sa = IRDA_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  IRDA_s1_readdata_from_sa <= IRDA_s1_readdata;
  internal_CPU_data_master_requests_IRDA_s1 <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 5) & std_logic_vector'("00000")) = std_logic_vector'("100000001000100000100000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign IRDA_s1_dataavailable_from_sa = IRDA_s1_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  IRDA_s1_dataavailable_from_sa <= IRDA_s1_dataavailable;
  --assign IRDA_s1_readyfordata_from_sa = IRDA_s1_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  IRDA_s1_readyfordata_from_sa <= IRDA_s1_readyfordata;
  --IRDA_s1_arb_share_counter set values, which is an e_mux
  IRDA_s1_arb_share_set_values <= std_logic_vector'("01");
  --IRDA_s1_non_bursting_master_requests mux, which is an e_mux
  IRDA_s1_non_bursting_master_requests <= internal_CPU_data_master_requests_IRDA_s1;
  --IRDA_s1_arb_share_counter_next_value assignment, which is an e_assign
  IRDA_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(IRDA_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (IRDA_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(IRDA_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (IRDA_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --IRDA_s1_allgrants all slave grants, which is an e_mux
  IRDA_s1_allgrants <= IRDA_s1_grant_vector;
  --IRDA_s1_end_xfer assignment, which is an e_assign
  IRDA_s1_end_xfer <= NOT ((IRDA_s1_waits_for_read OR IRDA_s1_waits_for_write));
  --IRDA_s1_arb_share_counter arbitration counter enable, which is an e_assign
  IRDA_s1_arb_counter_enable <= ((IRDA_s1_end_xfer AND IRDA_s1_allgrants)) OR ((IRDA_s1_end_xfer AND NOT IRDA_s1_non_bursting_master_requests));
  --IRDA_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      IRDA_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(IRDA_s1_arb_counter_enable) = '1' then 
        IRDA_s1_arb_share_counter <= IRDA_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --IRDA_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      IRDA_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((IRDA_s1_master_qreq_vector AND IRDA_s1_end_xfer)) OR ((IRDA_s1_end_xfer AND NOT IRDA_s1_non_bursting_master_requests)))) = '1' then 
        IRDA_s1_slavearbiterlockenable <= or_reduce(IRDA_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master IRDA/s1 arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= IRDA_s1_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --IRDA_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  IRDA_s1_slavearbiterlockenable2 <= or_reduce(IRDA_s1_arb_share_counter_next_value);
  --CPU/data_master IRDA/s1 arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= IRDA_s1_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --IRDA_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  IRDA_s1_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_IRDA_s1 <= internal_CPU_data_master_requests_IRDA_s1;
  --IRDA_s1_writedata mux, which is an e_mux
  IRDA_s1_writedata <= CPU_data_master_writedata (15 DOWNTO 0);
  --master is always granted when requested
  internal_CPU_data_master_granted_IRDA_s1 <= internal_CPU_data_master_qualified_request_IRDA_s1;
  --CPU/data_master saved-grant IRDA/s1, which is an e_assign
  CPU_data_master_saved_grant_IRDA_s1 <= internal_CPU_data_master_requests_IRDA_s1;
  --allow new arb cycle for IRDA/s1, which is an e_assign
  IRDA_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  IRDA_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  IRDA_s1_master_qreq_vector <= std_logic'('1');
  IRDA_s1_begintransfer <= IRDA_s1_begins_xfer;
  --IRDA_s1_reset_n assignment, which is an e_assign
  IRDA_s1_reset_n <= reset_n;
  IRDA_s1_chipselect <= internal_CPU_data_master_granted_IRDA_s1;
  --IRDA_s1_firsttransfer first transaction, which is an e_assign
  IRDA_s1_firsttransfer <= NOT ((IRDA_s1_slavearbiterlockenable AND IRDA_s1_any_continuerequest));
  --IRDA_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  IRDA_s1_beginbursttransfer_internal <= IRDA_s1_begins_xfer AND IRDA_s1_firsttransfer;
  --~IRDA_s1_read_n assignment, which is an e_mux
  IRDA_s1_read_n <= NOT ((internal_CPU_data_master_granted_IRDA_s1 AND CPU_data_master_read));
  --~IRDA_s1_write_n assignment, which is an e_mux
  IRDA_s1_write_n <= NOT ((internal_CPU_data_master_granted_IRDA_s1 AND CPU_data_master_write));
  --IRDA_s1_address mux, which is an e_mux
  IRDA_s1_address <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 3);
  --d1_IRDA_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_IRDA_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_IRDA_s1_end_xfer <= IRDA_s1_end_xfer;
      end if;
    end if;

  end process;

  --IRDA_s1_waits_for_read in a cycle, which is an e_mux
  IRDA_s1_waits_for_read <= IRDA_s1_in_a_read_cycle AND IRDA_s1_begins_xfer;
  --IRDA_s1_in_a_read_cycle assignment, which is an e_assign
  IRDA_s1_in_a_read_cycle <= internal_CPU_data_master_granted_IRDA_s1 AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= IRDA_s1_in_a_read_cycle;
  --IRDA_s1_waits_for_write in a cycle, which is an e_mux
  IRDA_s1_waits_for_write <= IRDA_s1_in_a_write_cycle AND IRDA_s1_begins_xfer;
  --IRDA_s1_in_a_write_cycle assignment, which is an e_assign
  IRDA_s1_in_a_write_cycle <= internal_CPU_data_master_granted_IRDA_s1 AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= IRDA_s1_in_a_write_cycle;
  wait_for_IRDA_s1_counter <= std_logic'('0');
  --assign IRDA_s1_irq_from_sa = IRDA_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  IRDA_s1_irq_from_sa <= IRDA_s1_irq;
  --vhdl renameroo for output signals
  CPU_data_master_granted_IRDA_s1 <= internal_CPU_data_master_granted_IRDA_s1;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_IRDA_s1 <= internal_CPU_data_master_qualified_request_IRDA_s1;
  --vhdl renameroo for output signals
  CPU_data_master_requests_IRDA_s1 <= internal_CPU_data_master_requests_IRDA_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity JTAG_avalon_jtag_slave_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal JTAG_avalon_jtag_slave_dataavailable : IN STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_irq : IN STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal JTAG_avalon_jtag_slave_readyfordata : IN STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_waitrequest : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                 signal CPU_data_master_requests_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_address : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_chipselect : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_dataavailable_from_sa : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_irq_from_sa : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_read_n : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal JTAG_avalon_jtag_slave_readyfordata_from_sa : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_reset_n : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_waitrequest_from_sa : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_write_n : OUT STD_LOGIC;
                 signal JTAG_avalon_jtag_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_JTAG_avalon_jtag_slave_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of JTAG_avalon_jtag_slave_arbitrator : entity is FALSE;
end entity JTAG_avalon_jtag_slave_arbitrator;


architecture europa of JTAG_avalon_jtag_slave_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_allgrants :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_any_continuerequest :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_arb_counter_enable :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_begins_xfer :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_end_xfer :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_firsttransfer :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_grant_vector :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_in_a_read_cycle :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_in_a_write_cycle :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_master_qreq_vector :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_non_bursting_master_requests :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_slavearbiterlockenable :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_waits_for_read :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal internal_CPU_data_master_requests_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal internal_JTAG_avalon_jtag_slave_waitrequest_from_sa :  STD_LOGIC;
                signal wait_for_JTAG_avalon_jtag_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT JTAG_avalon_jtag_slave_end_xfer;
      end if;
    end if;

  end process;

  JTAG_avalon_jtag_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_JTAG_avalon_jtag_slave);
  --assign JTAG_avalon_jtag_slave_readdata_from_sa = JTAG_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  JTAG_avalon_jtag_slave_readdata_from_sa <= JTAG_avalon_jtag_slave_readdata;
  internal_CPU_data_master_requests_JTAG_avalon_jtag_slave <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100000001000100010010000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign JTAG_avalon_jtag_slave_dataavailable_from_sa = JTAG_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  JTAG_avalon_jtag_slave_dataavailable_from_sa <= JTAG_avalon_jtag_slave_dataavailable;
  --assign JTAG_avalon_jtag_slave_readyfordata_from_sa = JTAG_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  JTAG_avalon_jtag_slave_readyfordata_from_sa <= JTAG_avalon_jtag_slave_readyfordata;
  --assign JTAG_avalon_jtag_slave_waitrequest_from_sa = JTAG_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_JTAG_avalon_jtag_slave_waitrequest_from_sa <= JTAG_avalon_jtag_slave_waitrequest;
  --JTAG_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  JTAG_avalon_jtag_slave_arb_share_set_values <= std_logic_vector'("01");
  --JTAG_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  JTAG_avalon_jtag_slave_non_bursting_master_requests <= internal_CPU_data_master_requests_JTAG_avalon_jtag_slave;
  --JTAG_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  JTAG_avalon_jtag_slave_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(JTAG_avalon_jtag_slave_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (JTAG_avalon_jtag_slave_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(JTAG_avalon_jtag_slave_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (JTAG_avalon_jtag_slave_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --JTAG_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  JTAG_avalon_jtag_slave_allgrants <= JTAG_avalon_jtag_slave_grant_vector;
  --JTAG_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  JTAG_avalon_jtag_slave_end_xfer <= NOT ((JTAG_avalon_jtag_slave_waits_for_read OR JTAG_avalon_jtag_slave_waits_for_write));
  --JTAG_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  JTAG_avalon_jtag_slave_arb_counter_enable <= ((JTAG_avalon_jtag_slave_end_xfer AND JTAG_avalon_jtag_slave_allgrants)) OR ((JTAG_avalon_jtag_slave_end_xfer AND NOT JTAG_avalon_jtag_slave_non_bursting_master_requests));
  --JTAG_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      JTAG_avalon_jtag_slave_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(JTAG_avalon_jtag_slave_arb_counter_enable) = '1' then 
        JTAG_avalon_jtag_slave_arb_share_counter <= JTAG_avalon_jtag_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --JTAG_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      JTAG_avalon_jtag_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((JTAG_avalon_jtag_slave_master_qreq_vector AND JTAG_avalon_jtag_slave_end_xfer)) OR ((JTAG_avalon_jtag_slave_end_xfer AND NOT JTAG_avalon_jtag_slave_non_bursting_master_requests)))) = '1' then 
        JTAG_avalon_jtag_slave_slavearbiterlockenable <= or_reduce(JTAG_avalon_jtag_slave_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master JTAG/avalon_jtag_slave arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= JTAG_avalon_jtag_slave_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --JTAG_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  JTAG_avalon_jtag_slave_slavearbiterlockenable2 <= or_reduce(JTAG_avalon_jtag_slave_arb_share_counter_next_value);
  --CPU/data_master JTAG/avalon_jtag_slave arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= JTAG_avalon_jtag_slave_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --JTAG_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  JTAG_avalon_jtag_slave_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_JTAG_avalon_jtag_slave <= internal_CPU_data_master_requests_JTAG_avalon_jtag_slave AND NOT ((((CPU_data_master_read AND (NOT CPU_data_master_waitrequest))) OR (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write))));
  --JTAG_avalon_jtag_slave_writedata mux, which is an e_mux
  JTAG_avalon_jtag_slave_writedata <= CPU_data_master_writedata;
  --master is always granted when requested
  internal_CPU_data_master_granted_JTAG_avalon_jtag_slave <= internal_CPU_data_master_qualified_request_JTAG_avalon_jtag_slave;
  --CPU/data_master saved-grant JTAG/avalon_jtag_slave, which is an e_assign
  CPU_data_master_saved_grant_JTAG_avalon_jtag_slave <= internal_CPU_data_master_requests_JTAG_avalon_jtag_slave;
  --allow new arb cycle for JTAG/avalon_jtag_slave, which is an e_assign
  JTAG_avalon_jtag_slave_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  JTAG_avalon_jtag_slave_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  JTAG_avalon_jtag_slave_master_qreq_vector <= std_logic'('1');
  --JTAG_avalon_jtag_slave_reset_n assignment, which is an e_assign
  JTAG_avalon_jtag_slave_reset_n <= reset_n;
  JTAG_avalon_jtag_slave_chipselect <= internal_CPU_data_master_granted_JTAG_avalon_jtag_slave;
  --JTAG_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  JTAG_avalon_jtag_slave_firsttransfer <= NOT ((JTAG_avalon_jtag_slave_slavearbiterlockenable AND JTAG_avalon_jtag_slave_any_continuerequest));
  --JTAG_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  JTAG_avalon_jtag_slave_beginbursttransfer_internal <= JTAG_avalon_jtag_slave_begins_xfer AND JTAG_avalon_jtag_slave_firsttransfer;
  --~JTAG_avalon_jtag_slave_read_n assignment, which is an e_mux
  JTAG_avalon_jtag_slave_read_n <= NOT ((internal_CPU_data_master_granted_JTAG_avalon_jtag_slave AND CPU_data_master_read));
  --~JTAG_avalon_jtag_slave_write_n assignment, which is an e_mux
  JTAG_avalon_jtag_slave_write_n <= NOT ((internal_CPU_data_master_granted_JTAG_avalon_jtag_slave AND CPU_data_master_write));
  --JTAG_avalon_jtag_slave_address mux, which is an e_mux
  JTAG_avalon_jtag_slave_address <= Vector_To_Std_Logic(A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")));
  --d1_JTAG_avalon_jtag_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_JTAG_avalon_jtag_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_JTAG_avalon_jtag_slave_end_xfer <= JTAG_avalon_jtag_slave_end_xfer;
      end if;
    end if;

  end process;

  --JTAG_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  JTAG_avalon_jtag_slave_waits_for_read <= JTAG_avalon_jtag_slave_in_a_read_cycle AND internal_JTAG_avalon_jtag_slave_waitrequest_from_sa;
  --JTAG_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  JTAG_avalon_jtag_slave_in_a_read_cycle <= internal_CPU_data_master_granted_JTAG_avalon_jtag_slave AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= JTAG_avalon_jtag_slave_in_a_read_cycle;
  --JTAG_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  JTAG_avalon_jtag_slave_waits_for_write <= JTAG_avalon_jtag_slave_in_a_write_cycle AND internal_JTAG_avalon_jtag_slave_waitrequest_from_sa;
  --JTAG_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  JTAG_avalon_jtag_slave_in_a_write_cycle <= internal_CPU_data_master_granted_JTAG_avalon_jtag_slave AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= JTAG_avalon_jtag_slave_in_a_write_cycle;
  wait_for_JTAG_avalon_jtag_slave_counter <= std_logic'('0');
  --assign JTAG_avalon_jtag_slave_irq_from_sa = JTAG_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  JTAG_avalon_jtag_slave_irq_from_sa <= JTAG_avalon_jtag_slave_irq;
  --vhdl renameroo for output signals
  CPU_data_master_granted_JTAG_avalon_jtag_slave <= internal_CPU_data_master_granted_JTAG_avalon_jtag_slave;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_JTAG_avalon_jtag_slave <= internal_CPU_data_master_qualified_request_JTAG_avalon_jtag_slave;
  --vhdl renameroo for output signals
  CPU_data_master_requests_JTAG_avalon_jtag_slave <= internal_CPU_data_master_requests_JTAG_avalon_jtag_slave;
  --vhdl renameroo for output signals
  JTAG_avalon_jtag_slave_waitrequest_from_sa <= internal_JTAG_avalon_jtag_slave_waitrequest_from_sa;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity KEYS_s1_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal KEYS_s1_readdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_KEYS_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_KEYS_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_KEYS_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_requests_KEYS_s1 : OUT STD_LOGIC;
                 signal KEYS_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal KEYS_s1_chipselect : OUT STD_LOGIC;
                 signal KEYS_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal KEYS_s1_reset_n : OUT STD_LOGIC;
                 signal KEYS_s1_write_n : OUT STD_LOGIC;
                 signal KEYS_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal d1_KEYS_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of KEYS_s1_arbitrator : entity is FALSE;
end entity KEYS_s1_arbitrator;


architecture europa of KEYS_s1_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_KEYS_s1 :  STD_LOGIC;
                signal KEYS_s1_allgrants :  STD_LOGIC;
                signal KEYS_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal KEYS_s1_any_continuerequest :  STD_LOGIC;
                signal KEYS_s1_arb_counter_enable :  STD_LOGIC;
                signal KEYS_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal KEYS_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal KEYS_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal KEYS_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal KEYS_s1_begins_xfer :  STD_LOGIC;
                signal KEYS_s1_end_xfer :  STD_LOGIC;
                signal KEYS_s1_firsttransfer :  STD_LOGIC;
                signal KEYS_s1_grant_vector :  STD_LOGIC;
                signal KEYS_s1_in_a_read_cycle :  STD_LOGIC;
                signal KEYS_s1_in_a_write_cycle :  STD_LOGIC;
                signal KEYS_s1_master_qreq_vector :  STD_LOGIC;
                signal KEYS_s1_non_bursting_master_requests :  STD_LOGIC;
                signal KEYS_s1_slavearbiterlockenable :  STD_LOGIC;
                signal KEYS_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal KEYS_s1_waits_for_read :  STD_LOGIC;
                signal KEYS_s1_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_KEYS_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_KEYS_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_requests_KEYS_s1 :  STD_LOGIC;
                signal wait_for_KEYS_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT KEYS_s1_end_xfer;
      end if;
    end if;

  end process;

  KEYS_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_KEYS_s1);
  --assign KEYS_s1_readdata_from_sa = KEYS_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  KEYS_s1_readdata_from_sa <= KEYS_s1_readdata;
  internal_CPU_data_master_requests_KEYS_s1 <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000001000100001110000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --KEYS_s1_arb_share_counter set values, which is an e_mux
  KEYS_s1_arb_share_set_values <= std_logic_vector'("01");
  --KEYS_s1_non_bursting_master_requests mux, which is an e_mux
  KEYS_s1_non_bursting_master_requests <= internal_CPU_data_master_requests_KEYS_s1;
  --KEYS_s1_arb_share_counter_next_value assignment, which is an e_assign
  KEYS_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(KEYS_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (KEYS_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(KEYS_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (KEYS_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --KEYS_s1_allgrants all slave grants, which is an e_mux
  KEYS_s1_allgrants <= KEYS_s1_grant_vector;
  --KEYS_s1_end_xfer assignment, which is an e_assign
  KEYS_s1_end_xfer <= NOT ((KEYS_s1_waits_for_read OR KEYS_s1_waits_for_write));
  --KEYS_s1_arb_share_counter arbitration counter enable, which is an e_assign
  KEYS_s1_arb_counter_enable <= ((KEYS_s1_end_xfer AND KEYS_s1_allgrants)) OR ((KEYS_s1_end_xfer AND NOT KEYS_s1_non_bursting_master_requests));
  --KEYS_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      KEYS_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(KEYS_s1_arb_counter_enable) = '1' then 
        KEYS_s1_arb_share_counter <= KEYS_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --KEYS_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      KEYS_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((KEYS_s1_master_qreq_vector AND KEYS_s1_end_xfer)) OR ((KEYS_s1_end_xfer AND NOT KEYS_s1_non_bursting_master_requests)))) = '1' then 
        KEYS_s1_slavearbiterlockenable <= or_reduce(KEYS_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master KEYS/s1 arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= KEYS_s1_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --KEYS_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  KEYS_s1_slavearbiterlockenable2 <= or_reduce(KEYS_s1_arb_share_counter_next_value);
  --CPU/data_master KEYS/s1 arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= KEYS_s1_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --KEYS_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  KEYS_s1_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_KEYS_s1 <= internal_CPU_data_master_requests_KEYS_s1 AND NOT (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write));
  --KEYS_s1_writedata mux, which is an e_mux
  KEYS_s1_writedata <= CPU_data_master_writedata (3 DOWNTO 0);
  --master is always granted when requested
  internal_CPU_data_master_granted_KEYS_s1 <= internal_CPU_data_master_qualified_request_KEYS_s1;
  --CPU/data_master saved-grant KEYS/s1, which is an e_assign
  CPU_data_master_saved_grant_KEYS_s1 <= internal_CPU_data_master_requests_KEYS_s1;
  --allow new arb cycle for KEYS/s1, which is an e_assign
  KEYS_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  KEYS_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  KEYS_s1_master_qreq_vector <= std_logic'('1');
  --KEYS_s1_reset_n assignment, which is an e_assign
  KEYS_s1_reset_n <= reset_n;
  KEYS_s1_chipselect <= internal_CPU_data_master_granted_KEYS_s1;
  --KEYS_s1_firsttransfer first transaction, which is an e_assign
  KEYS_s1_firsttransfer <= NOT ((KEYS_s1_slavearbiterlockenable AND KEYS_s1_any_continuerequest));
  --KEYS_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  KEYS_s1_beginbursttransfer_internal <= KEYS_s1_begins_xfer AND KEYS_s1_firsttransfer;
  --~KEYS_s1_write_n assignment, which is an e_mux
  KEYS_s1_write_n <= NOT ((internal_CPU_data_master_granted_KEYS_s1 AND CPU_data_master_write));
  --KEYS_s1_address mux, which is an e_mux
  KEYS_s1_address <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_KEYS_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_KEYS_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_KEYS_s1_end_xfer <= KEYS_s1_end_xfer;
      end if;
    end if;

  end process;

  --KEYS_s1_waits_for_read in a cycle, which is an e_mux
  KEYS_s1_waits_for_read <= KEYS_s1_in_a_read_cycle AND KEYS_s1_begins_xfer;
  --KEYS_s1_in_a_read_cycle assignment, which is an e_assign
  KEYS_s1_in_a_read_cycle <= internal_CPU_data_master_granted_KEYS_s1 AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= KEYS_s1_in_a_read_cycle;
  --KEYS_s1_waits_for_write in a cycle, which is an e_mux
  KEYS_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(KEYS_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --KEYS_s1_in_a_write_cycle assignment, which is an e_assign
  KEYS_s1_in_a_write_cycle <= internal_CPU_data_master_granted_KEYS_s1 AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= KEYS_s1_in_a_write_cycle;
  wait_for_KEYS_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  CPU_data_master_granted_KEYS_s1 <= internal_CPU_data_master_granted_KEYS_s1;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_KEYS_s1 <= internal_CPU_data_master_qualified_request_KEYS_s1;
  --vhdl renameroo for output signals
  CPU_data_master_requests_KEYS_s1 <= internal_CPU_data_master_requests_KEYS_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LCD_control_slave_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal LCD_control_slave_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_LCD_control_slave : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_LCD_control_slave : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_LCD_control_slave : OUT STD_LOGIC;
                 signal CPU_data_master_requests_LCD_control_slave : OUT STD_LOGIC;
                 signal LCD_control_slave_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal LCD_control_slave_begintransfer : OUT STD_LOGIC;
                 signal LCD_control_slave_read : OUT STD_LOGIC;
                 signal LCD_control_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal LCD_control_slave_wait_counter_eq_0 : OUT STD_LOGIC;
                 signal LCD_control_slave_wait_counter_eq_1 : OUT STD_LOGIC;
                 signal LCD_control_slave_write : OUT STD_LOGIC;
                 signal LCD_control_slave_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal d1_LCD_control_slave_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of LCD_control_slave_arbitrator : entity is FALSE;
end entity LCD_control_slave_arbitrator;


architecture europa of LCD_control_slave_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_LCD_control_slave :  STD_LOGIC;
                signal LCD_control_slave_allgrants :  STD_LOGIC;
                signal LCD_control_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal LCD_control_slave_any_continuerequest :  STD_LOGIC;
                signal LCD_control_slave_arb_counter_enable :  STD_LOGIC;
                signal LCD_control_slave_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal LCD_control_slave_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal LCD_control_slave_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal LCD_control_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal LCD_control_slave_begins_xfer :  STD_LOGIC;
                signal LCD_control_slave_counter_load_value :  STD_LOGIC_VECTOR (6 DOWNTO 0);
                signal LCD_control_slave_end_xfer :  STD_LOGIC;
                signal LCD_control_slave_firsttransfer :  STD_LOGIC;
                signal LCD_control_slave_grant_vector :  STD_LOGIC;
                signal LCD_control_slave_in_a_read_cycle :  STD_LOGIC;
                signal LCD_control_slave_in_a_write_cycle :  STD_LOGIC;
                signal LCD_control_slave_master_qreq_vector :  STD_LOGIC;
                signal LCD_control_slave_non_bursting_master_requests :  STD_LOGIC;
                signal LCD_control_slave_pretend_byte_enable :  STD_LOGIC;
                signal LCD_control_slave_slavearbiterlockenable :  STD_LOGIC;
                signal LCD_control_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal LCD_control_slave_wait_counter :  STD_LOGIC_VECTOR (6 DOWNTO 0);
                signal LCD_control_slave_waits_for_read :  STD_LOGIC;
                signal LCD_control_slave_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_LCD_control_slave :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_LCD_control_slave :  STD_LOGIC;
                signal internal_CPU_data_master_requests_LCD_control_slave :  STD_LOGIC;
                signal internal_LCD_control_slave_wait_counter_eq_0 :  STD_LOGIC;
                signal wait_for_LCD_control_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT LCD_control_slave_end_xfer;
      end if;
    end if;

  end process;

  LCD_control_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_LCD_control_slave);
  --assign LCD_control_slave_readdata_from_sa = LCD_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  LCD_control_slave_readdata_from_sa <= LCD_control_slave_readdata;
  internal_CPU_data_master_requests_LCD_control_slave <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000001000100001100000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --LCD_control_slave_arb_share_counter set values, which is an e_mux
  LCD_control_slave_arb_share_set_values <= std_logic_vector'("01");
  --LCD_control_slave_non_bursting_master_requests mux, which is an e_mux
  LCD_control_slave_non_bursting_master_requests <= internal_CPU_data_master_requests_LCD_control_slave;
  --LCD_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  LCD_control_slave_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(LCD_control_slave_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (LCD_control_slave_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(LCD_control_slave_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (LCD_control_slave_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --LCD_control_slave_allgrants all slave grants, which is an e_mux
  LCD_control_slave_allgrants <= LCD_control_slave_grant_vector;
  --LCD_control_slave_end_xfer assignment, which is an e_assign
  LCD_control_slave_end_xfer <= NOT ((LCD_control_slave_waits_for_read OR LCD_control_slave_waits_for_write));
  --LCD_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  LCD_control_slave_arb_counter_enable <= ((LCD_control_slave_end_xfer AND LCD_control_slave_allgrants)) OR ((LCD_control_slave_end_xfer AND NOT LCD_control_slave_non_bursting_master_requests));
  --LCD_control_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      LCD_control_slave_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(LCD_control_slave_arb_counter_enable) = '1' then 
        LCD_control_slave_arb_share_counter <= LCD_control_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --LCD_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      LCD_control_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((LCD_control_slave_master_qreq_vector AND LCD_control_slave_end_xfer)) OR ((LCD_control_slave_end_xfer AND NOT LCD_control_slave_non_bursting_master_requests)))) = '1' then 
        LCD_control_slave_slavearbiterlockenable <= or_reduce(LCD_control_slave_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master LCD/control_slave arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= LCD_control_slave_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --LCD_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  LCD_control_slave_slavearbiterlockenable2 <= or_reduce(LCD_control_slave_arb_share_counter_next_value);
  --CPU/data_master LCD/control_slave arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= LCD_control_slave_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --LCD_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  LCD_control_slave_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_LCD_control_slave <= internal_CPU_data_master_requests_LCD_control_slave;
  --LCD_control_slave_writedata mux, which is an e_mux
  LCD_control_slave_writedata <= CPU_data_master_writedata (7 DOWNTO 0);
  --master is always granted when requested
  internal_CPU_data_master_granted_LCD_control_slave <= internal_CPU_data_master_qualified_request_LCD_control_slave;
  --CPU/data_master saved-grant LCD/control_slave, which is an e_assign
  CPU_data_master_saved_grant_LCD_control_slave <= internal_CPU_data_master_requests_LCD_control_slave;
  --allow new arb cycle for LCD/control_slave, which is an e_assign
  LCD_control_slave_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  LCD_control_slave_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  LCD_control_slave_master_qreq_vector <= std_logic'('1');
  LCD_control_slave_begintransfer <= LCD_control_slave_begins_xfer;
  --LCD_control_slave_firsttransfer first transaction, which is an e_assign
  LCD_control_slave_firsttransfer <= NOT ((LCD_control_slave_slavearbiterlockenable AND LCD_control_slave_any_continuerequest));
  --LCD_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  LCD_control_slave_beginbursttransfer_internal <= LCD_control_slave_begins_xfer AND LCD_control_slave_firsttransfer;
  --LCD_control_slave_read assignment, which is an e_mux
  LCD_control_slave_read <= (((internal_CPU_data_master_granted_LCD_control_slave AND CPU_data_master_read)) AND NOT LCD_control_slave_begins_xfer) AND to_std_logic((((std_logic_vector'("0000000000000000000000000") & (LCD_control_slave_wait_counter))<std_logic_vector'("00000000000000000000000000010111"))));
  --LCD_control_slave_write assignment, which is an e_mux
  LCD_control_slave_write <= (((((internal_CPU_data_master_granted_LCD_control_slave AND CPU_data_master_write)) AND NOT LCD_control_slave_begins_xfer) AND to_std_logic((((std_logic_vector'("0000000000000000000000000") & (LCD_control_slave_wait_counter))>=std_logic_vector'("00000000000000000000000000010111"))))) AND to_std_logic((((std_logic_vector'("0000000000000000000000000") & (LCD_control_slave_wait_counter))<std_logic_vector'("00000000000000000000000000101110"))))) AND LCD_control_slave_pretend_byte_enable;
  --LCD_control_slave_address mux, which is an e_mux
  LCD_control_slave_address <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_LCD_control_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_LCD_control_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_LCD_control_slave_end_xfer <= LCD_control_slave_end_xfer;
      end if;
    end if;

  end process;

  --LCD_control_slave_wait_counter_eq_1 assignment, which is an e_assign
  LCD_control_slave_wait_counter_eq_1 <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (LCD_control_slave_wait_counter)) = std_logic_vector'("00000000000000000000000000000001")));
  --LCD_control_slave_waits_for_read in a cycle, which is an e_mux
  LCD_control_slave_waits_for_read <= LCD_control_slave_in_a_read_cycle AND wait_for_LCD_control_slave_counter;
  --LCD_control_slave_in_a_read_cycle assignment, which is an e_assign
  LCD_control_slave_in_a_read_cycle <= internal_CPU_data_master_granted_LCD_control_slave AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= LCD_control_slave_in_a_read_cycle;
  --LCD_control_slave_waits_for_write in a cycle, which is an e_mux
  LCD_control_slave_waits_for_write <= LCD_control_slave_in_a_write_cycle AND wait_for_LCD_control_slave_counter;
  --LCD_control_slave_in_a_write_cycle assignment, which is an e_assign
  LCD_control_slave_in_a_write_cycle <= internal_CPU_data_master_granted_LCD_control_slave AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= LCD_control_slave_in_a_write_cycle;
  internal_LCD_control_slave_wait_counter_eq_0 <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (LCD_control_slave_wait_counter)) = std_logic_vector'("00000000000000000000000000000000")));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      LCD_control_slave_wait_counter <= std_logic_vector'("0000000");
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        LCD_control_slave_wait_counter <= LCD_control_slave_counter_load_value;
      end if;
    end if;

  end process;

  LCD_control_slave_counter_load_value <= A_EXT (A_WE_StdLogicVector((std_logic'(((LCD_control_slave_in_a_read_cycle AND LCD_control_slave_begins_xfer))) = '1'), std_logic_vector'("000000000000000000000000000101100"), A_WE_StdLogicVector((std_logic'(((LCD_control_slave_in_a_write_cycle AND LCD_control_slave_begins_xfer))) = '1'), std_logic_vector'("000000000000000000000000001000011"), A_WE_StdLogicVector((std_logic'((NOT internal_LCD_control_slave_wait_counter_eq_0)) = '1'), ((std_logic_vector'("00000000000000000000000000") & (LCD_control_slave_wait_counter)) - std_logic_vector'("000000000000000000000000000000001")), std_logic_vector'("000000000000000000000000000000000")))), 7);
  wait_for_LCD_control_slave_counter <= LCD_control_slave_begins_xfer OR NOT internal_LCD_control_slave_wait_counter_eq_0;
  --LCD_control_slave_pretend_byte_enable byte enable port mux, which is an e_mux
  LCD_control_slave_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_LCD_control_slave)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (CPU_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  CPU_data_master_granted_LCD_control_slave <= internal_CPU_data_master_granted_LCD_control_slave;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_LCD_control_slave <= internal_CPU_data_master_qualified_request_LCD_control_slave;
  --vhdl renameroo for output signals
  CPU_data_master_requests_LCD_control_slave <= internal_CPU_data_master_requests_LCD_control_slave;
  --vhdl renameroo for output signals
  LCD_control_slave_wait_counter_eq_0 <= internal_LCD_control_slave_wait_counter_eq_0;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity PLL_s1_arbitrator is 
        port (
              -- inputs:
                 signal PLL_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal PLL_s1_resetrequest : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal clock_1_out_address_to_slave : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clock_1_out_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal clock_1_out_read : IN STD_LOGIC;
                 signal clock_1_out_write : IN STD_LOGIC;
                 signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal PLL_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal PLL_s1_chipselect : OUT STD_LOGIC;
                 signal PLL_s1_read : OUT STD_LOGIC;
                 signal PLL_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal PLL_s1_reset_n : OUT STD_LOGIC;
                 signal PLL_s1_resetrequest_from_sa : OUT STD_LOGIC;
                 signal PLL_s1_write : OUT STD_LOGIC;
                 signal PLL_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clock_1_out_granted_PLL_s1 : OUT STD_LOGIC;
                 signal clock_1_out_qualified_request_PLL_s1 : OUT STD_LOGIC;
                 signal clock_1_out_read_data_valid_PLL_s1 : OUT STD_LOGIC;
                 signal clock_1_out_requests_PLL_s1 : OUT STD_LOGIC;
                 signal d1_PLL_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of PLL_s1_arbitrator : entity is FALSE;
end entity PLL_s1_arbitrator;


architecture europa of PLL_s1_arbitrator is
                signal PLL_s1_allgrants :  STD_LOGIC;
                signal PLL_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal PLL_s1_any_continuerequest :  STD_LOGIC;
                signal PLL_s1_arb_counter_enable :  STD_LOGIC;
                signal PLL_s1_arb_share_counter :  STD_LOGIC;
                signal PLL_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal PLL_s1_arb_share_set_values :  STD_LOGIC;
                signal PLL_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal PLL_s1_begins_xfer :  STD_LOGIC;
                signal PLL_s1_end_xfer :  STD_LOGIC;
                signal PLL_s1_firsttransfer :  STD_LOGIC;
                signal PLL_s1_grant_vector :  STD_LOGIC;
                signal PLL_s1_in_a_read_cycle :  STD_LOGIC;
                signal PLL_s1_in_a_write_cycle :  STD_LOGIC;
                signal PLL_s1_master_qreq_vector :  STD_LOGIC;
                signal PLL_s1_non_bursting_master_requests :  STD_LOGIC;
                signal PLL_s1_slavearbiterlockenable :  STD_LOGIC;
                signal PLL_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal PLL_s1_waits_for_read :  STD_LOGIC;
                signal PLL_s1_waits_for_write :  STD_LOGIC;
                signal clock_1_out_arbiterlock :  STD_LOGIC;
                signal clock_1_out_arbiterlock2 :  STD_LOGIC;
                signal clock_1_out_continuerequest :  STD_LOGIC;
                signal clock_1_out_saved_grant_PLL_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_1_out_granted_PLL_s1 :  STD_LOGIC;
                signal internal_clock_1_out_qualified_request_PLL_s1 :  STD_LOGIC;
                signal internal_clock_1_out_requests_PLL_s1 :  STD_LOGIC;
                signal wait_for_PLL_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT PLL_s1_end_xfer;
      end if;
    end if;

  end process;

  PLL_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_1_out_qualified_request_PLL_s1);
  --assign PLL_s1_readdata_from_sa = PLL_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  PLL_s1_readdata_from_sa <= PLL_s1_readdata;
  internal_clock_1_out_requests_PLL_s1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_1_out_read OR clock_1_out_write)))))));
  --PLL_s1_arb_share_counter set values, which is an e_mux
  PLL_s1_arb_share_set_values <= std_logic'('1');
  --PLL_s1_non_bursting_master_requests mux, which is an e_mux
  PLL_s1_non_bursting_master_requests <= internal_clock_1_out_requests_PLL_s1;
  --PLL_s1_arb_share_counter_next_value assignment, which is an e_assign
  PLL_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(PLL_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(PLL_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(PLL_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(PLL_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --PLL_s1_allgrants all slave grants, which is an e_mux
  PLL_s1_allgrants <= PLL_s1_grant_vector;
  --PLL_s1_end_xfer assignment, which is an e_assign
  PLL_s1_end_xfer <= NOT ((PLL_s1_waits_for_read OR PLL_s1_waits_for_write));
  --PLL_s1_arb_share_counter arbitration counter enable, which is an e_assign
  PLL_s1_arb_counter_enable <= ((PLL_s1_end_xfer AND PLL_s1_allgrants)) OR ((PLL_s1_end_xfer AND NOT PLL_s1_non_bursting_master_requests));
  --PLL_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      PLL_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(PLL_s1_arb_counter_enable) = '1' then 
        PLL_s1_arb_share_counter <= PLL_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --PLL_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      PLL_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((PLL_s1_master_qreq_vector AND PLL_s1_end_xfer)) OR ((PLL_s1_end_xfer AND NOT PLL_s1_non_bursting_master_requests)))) = '1' then 
        PLL_s1_slavearbiterlockenable <= PLL_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_1/out PLL/s1 arbiterlock, which is an e_assign
  clock_1_out_arbiterlock <= PLL_s1_slavearbiterlockenable AND clock_1_out_continuerequest;
  --PLL_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  PLL_s1_slavearbiterlockenable2 <= PLL_s1_arb_share_counter_next_value;
  --clock_1/out PLL/s1 arbiterlock2, which is an e_assign
  clock_1_out_arbiterlock2 <= PLL_s1_slavearbiterlockenable2 AND clock_1_out_continuerequest;
  --PLL_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  PLL_s1_any_continuerequest <= std_logic'('1');
  --clock_1_out_continuerequest continued request, which is an e_assign
  clock_1_out_continuerequest <= std_logic'('1');
  internal_clock_1_out_qualified_request_PLL_s1 <= internal_clock_1_out_requests_PLL_s1;
  --PLL_s1_writedata mux, which is an e_mux
  PLL_s1_writedata <= clock_1_out_writedata;
  --master is always granted when requested
  internal_clock_1_out_granted_PLL_s1 <= internal_clock_1_out_qualified_request_PLL_s1;
  --clock_1/out saved-grant PLL/s1, which is an e_assign
  clock_1_out_saved_grant_PLL_s1 <= internal_clock_1_out_requests_PLL_s1;
  --allow new arb cycle for PLL/s1, which is an e_assign
  PLL_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  PLL_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  PLL_s1_master_qreq_vector <= std_logic'('1');
  --PLL_s1_reset_n assignment, which is an e_assign
  PLL_s1_reset_n <= reset_n;
  --assign PLL_s1_resetrequest_from_sa = PLL_s1_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  PLL_s1_resetrequest_from_sa <= PLL_s1_resetrequest;
  PLL_s1_chipselect <= internal_clock_1_out_granted_PLL_s1;
  --PLL_s1_firsttransfer first transaction, which is an e_assign
  PLL_s1_firsttransfer <= NOT ((PLL_s1_slavearbiterlockenable AND PLL_s1_any_continuerequest));
  --PLL_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  PLL_s1_beginbursttransfer_internal <= PLL_s1_begins_xfer AND PLL_s1_firsttransfer;
  --PLL_s1_read assignment, which is an e_mux
  PLL_s1_read <= internal_clock_1_out_granted_PLL_s1 AND clock_1_out_read;
  --PLL_s1_write assignment, which is an e_mux
  PLL_s1_write <= internal_clock_1_out_granted_PLL_s1 AND clock_1_out_write;
  --PLL_s1_address mux, which is an e_mux
  PLL_s1_address <= clock_1_out_nativeaddress;
  --d1_PLL_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_PLL_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_PLL_s1_end_xfer <= PLL_s1_end_xfer;
      end if;
    end if;

  end process;

  --PLL_s1_waits_for_read in a cycle, which is an e_mux
  PLL_s1_waits_for_read <= PLL_s1_in_a_read_cycle AND PLL_s1_begins_xfer;
  --PLL_s1_in_a_read_cycle assignment, which is an e_assign
  PLL_s1_in_a_read_cycle <= internal_clock_1_out_granted_PLL_s1 AND clock_1_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= PLL_s1_in_a_read_cycle;
  --PLL_s1_waits_for_write in a cycle, which is an e_mux
  PLL_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(PLL_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --PLL_s1_in_a_write_cycle assignment, which is an e_assign
  PLL_s1_in_a_write_cycle <= internal_clock_1_out_granted_PLL_s1 AND clock_1_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= PLL_s1_in_a_write_cycle;
  wait_for_PLL_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_1_out_granted_PLL_s1 <= internal_clock_1_out_granted_PLL_s1;
  --vhdl renameroo for output signals
  clock_1_out_qualified_request_PLL_s1 <= internal_clock_1_out_qualified_request_PLL_s1;
  --vhdl renameroo for output signals
  clock_1_out_requests_PLL_s1 <= internal_clock_1_out_requests_PLL_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module is 
        port (
              -- inputs:
                 signal clear_fifo : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal read : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal sync_reset : IN STD_LOGIC;
                 signal write : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC;
                 signal empty : OUT STD_LOGIC;
                 signal fifo_contains_ones_n : OUT STD_LOGIC;
                 signal full : OUT STD_LOGIC
              );
end entity rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module;


architecture europa of rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module is
                signal full_0 :  STD_LOGIC;
                signal full_1 :  STD_LOGIC;
                signal full_2 :  STD_LOGIC;
                signal full_3 :  STD_LOGIC;
                signal full_4 :  STD_LOGIC;
                signal full_5 :  STD_LOGIC;
                signal full_6 :  STD_LOGIC;
                signal full_7 :  STD_LOGIC;
                signal how_many_ones :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal one_count_minus_one :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal one_count_plus_one :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal p0_full_0 :  STD_LOGIC;
                signal p0_stage_0 :  STD_LOGIC;
                signal p1_full_1 :  STD_LOGIC;
                signal p1_stage_1 :  STD_LOGIC;
                signal p2_full_2 :  STD_LOGIC;
                signal p2_stage_2 :  STD_LOGIC;
                signal p3_full_3 :  STD_LOGIC;
                signal p3_stage_3 :  STD_LOGIC;
                signal p4_full_4 :  STD_LOGIC;
                signal p4_stage_4 :  STD_LOGIC;
                signal p5_full_5 :  STD_LOGIC;
                signal p5_stage_5 :  STD_LOGIC;
                signal p6_full_6 :  STD_LOGIC;
                signal p6_stage_6 :  STD_LOGIC;
                signal stage_0 :  STD_LOGIC;
                signal stage_1 :  STD_LOGIC;
                signal stage_2 :  STD_LOGIC;
                signal stage_3 :  STD_LOGIC;
                signal stage_4 :  STD_LOGIC;
                signal stage_5 :  STD_LOGIC;
                signal stage_6 :  STD_LOGIC;
                signal updated_one_count :  STD_LOGIC_VECTOR (3 DOWNTO 0);

begin

  data_out <= stage_0;
  full <= full_6;
  empty <= NOT(full_0);
  full_7 <= std_logic'('0');
  --data_6, which is an e_mux
  p6_stage_6 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_7 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
  --data_reg_6, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_6))))) = '1' then 
        if std_logic'(((sync_reset AND full_6) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_7))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_6 <= std_logic'('0');
        else
          stage_6 <= p6_stage_6;
        end if;
      end if;
    end if;

  end process;

  --control_6, which is an e_mux
  p6_full_6 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))), std_logic_vector'("00000000000000000000000000000000")));
  --control_reg_6, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_6 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_6 <= std_logic'('0');
        else
          full_6 <= p6_full_6;
        end if;
      end if;
    end if;

  end process;

  --data_5, which is an e_mux
  p5_stage_5 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_6 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_6);
  --data_reg_5, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_5))))) = '1' then 
        if std_logic'(((sync_reset AND full_5) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_6))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_5 <= std_logic'('0');
        else
          stage_5 <= p5_stage_5;
        end if;
      end if;
    end if;

  end process;

  --control_5, which is an e_mux
  p5_full_5 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_4, full_6);
  --control_reg_5, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_5 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_5 <= std_logic'('0');
        else
          full_5 <= p5_full_5;
        end if;
      end if;
    end if;

  end process;

  --data_4, which is an e_mux
  p4_stage_4 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_5 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_5);
  --data_reg_4, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_4))))) = '1' then 
        if std_logic'(((sync_reset AND full_4) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_4 <= std_logic'('0');
        else
          stage_4 <= p4_stage_4;
        end if;
      end if;
    end if;

  end process;

  --control_4, which is an e_mux
  p4_full_4 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_3, full_5);
  --control_reg_4, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_4 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_4 <= std_logic'('0');
        else
          full_4 <= p4_full_4;
        end if;
      end if;
    end if;

  end process;

  --data_3, which is an e_mux
  p3_stage_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_4 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_4);
  --data_reg_3, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_3))))) = '1' then 
        if std_logic'(((sync_reset AND full_3) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_4))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_3 <= std_logic'('0');
        else
          stage_3 <= p3_stage_3;
        end if;
      end if;
    end if;

  end process;

  --control_3, which is an e_mux
  p3_full_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_2, full_4);
  --control_reg_3, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_3 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_3 <= std_logic'('0');
        else
          full_3 <= p3_full_3;
        end if;
      end if;
    end if;

  end process;

  --data_2, which is an e_mux
  p2_stage_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_3 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_3);
  --data_reg_2, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_2))))) = '1' then 
        if std_logic'(((sync_reset AND full_2) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_2 <= std_logic'('0');
        else
          stage_2 <= p2_stage_2;
        end if;
      end if;
    end if;

  end process;

  --control_2, which is an e_mux
  p2_full_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_1, full_3);
  --control_reg_2, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_2 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_2 <= std_logic'('0');
        else
          full_2 <= p2_full_2;
        end if;
      end if;
    end if;

  end process;

  --data_1, which is an e_mux
  p1_stage_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_2);
  --data_reg_1, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then 
        if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_1 <= std_logic'('0');
        else
          stage_1 <= p1_stage_1;
        end if;
      end if;
    end if;

  end process;

  --control_1, which is an e_mux
  p1_full_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_0, full_2);
  --control_reg_1, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_1 <= std_logic'('0');
        else
          full_1 <= p1_full_1;
        end if;
      end if;
    end if;

  end process;

  --data_0, which is an e_mux
  p0_stage_0 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
  --data_reg_0, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_0 <= std_logic'('0');
        else
          stage_0 <= p0_stage_0;
        end if;
      end if;
    end if;

  end process;

  --control_0, which is an e_mux
  p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
  --control_reg_0, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_0 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'((clear_fifo AND NOT write)) = '1' then 
          full_0 <= std_logic'('0');
        else
          full_0 <= p0_full_0;
        end if;
      end if;
    end if;

  end process;

  one_count_plus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 4);
  one_count_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 4);
  --updated_one_count, which is an e_mux
  updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(data_in))), A_WE_StdLogicVector((std_logic'(((((read AND (data_in)) AND write) AND (stage_0)))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (data_in)))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (stage_0)))) = '1'), one_count_minus_one, how_many_ones))))))), 4);
  --counts how many ones in the data pipeline, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      how_many_ones <= std_logic_vector'("0000");
    elsif clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then 
        how_many_ones <= updated_one_count;
      end if;
    end if;

  end process;

  --this fifo contains ones in the data pipeline, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_contains_ones_n <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then 
        fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module is 
        port (
              -- inputs:
                 signal clear_fifo : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal read : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal sync_reset : IN STD_LOGIC;
                 signal write : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC;
                 signal empty : OUT STD_LOGIC;
                 signal fifo_contains_ones_n : OUT STD_LOGIC;
                 signal full : OUT STD_LOGIC
              );
end entity rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module;


architecture europa of rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module is
                signal full_0 :  STD_LOGIC;
                signal full_1 :  STD_LOGIC;
                signal full_2 :  STD_LOGIC;
                signal full_3 :  STD_LOGIC;
                signal full_4 :  STD_LOGIC;
                signal full_5 :  STD_LOGIC;
                signal full_6 :  STD_LOGIC;
                signal full_7 :  STD_LOGIC;
                signal how_many_ones :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal one_count_minus_one :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal one_count_plus_one :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal p0_full_0 :  STD_LOGIC;
                signal p0_stage_0 :  STD_LOGIC;
                signal p1_full_1 :  STD_LOGIC;
                signal p1_stage_1 :  STD_LOGIC;
                signal p2_full_2 :  STD_LOGIC;
                signal p2_stage_2 :  STD_LOGIC;
                signal p3_full_3 :  STD_LOGIC;
                signal p3_stage_3 :  STD_LOGIC;
                signal p4_full_4 :  STD_LOGIC;
                signal p4_stage_4 :  STD_LOGIC;
                signal p5_full_5 :  STD_LOGIC;
                signal p5_stage_5 :  STD_LOGIC;
                signal p6_full_6 :  STD_LOGIC;
                signal p6_stage_6 :  STD_LOGIC;
                signal stage_0 :  STD_LOGIC;
                signal stage_1 :  STD_LOGIC;
                signal stage_2 :  STD_LOGIC;
                signal stage_3 :  STD_LOGIC;
                signal stage_4 :  STD_LOGIC;
                signal stage_5 :  STD_LOGIC;
                signal stage_6 :  STD_LOGIC;
                signal updated_one_count :  STD_LOGIC_VECTOR (3 DOWNTO 0);

begin

  data_out <= stage_0;
  full <= full_6;
  empty <= NOT(full_0);
  full_7 <= std_logic'('0');
  --data_6, which is an e_mux
  p6_stage_6 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_7 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
  --data_reg_6, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_6))))) = '1' then 
        if std_logic'(((sync_reset AND full_6) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_7))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_6 <= std_logic'('0');
        else
          stage_6 <= p6_stage_6;
        end if;
      end if;
    end if;

  end process;

  --control_6, which is an e_mux
  p6_full_6 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))), std_logic_vector'("00000000000000000000000000000000")));
  --control_reg_6, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_6 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_6 <= std_logic'('0');
        else
          full_6 <= p6_full_6;
        end if;
      end if;
    end if;

  end process;

  --data_5, which is an e_mux
  p5_stage_5 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_6 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_6);
  --data_reg_5, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_5))))) = '1' then 
        if std_logic'(((sync_reset AND full_5) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_6))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_5 <= std_logic'('0');
        else
          stage_5 <= p5_stage_5;
        end if;
      end if;
    end if;

  end process;

  --control_5, which is an e_mux
  p5_full_5 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_4, full_6);
  --control_reg_5, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_5 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_5 <= std_logic'('0');
        else
          full_5 <= p5_full_5;
        end if;
      end if;
    end if;

  end process;

  --data_4, which is an e_mux
  p4_stage_4 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_5 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_5);
  --data_reg_4, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_4))))) = '1' then 
        if std_logic'(((sync_reset AND full_4) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_4 <= std_logic'('0');
        else
          stage_4 <= p4_stage_4;
        end if;
      end if;
    end if;

  end process;

  --control_4, which is an e_mux
  p4_full_4 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_3, full_5);
  --control_reg_4, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_4 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_4 <= std_logic'('0');
        else
          full_4 <= p4_full_4;
        end if;
      end if;
    end if;

  end process;

  --data_3, which is an e_mux
  p3_stage_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_4 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_4);
  --data_reg_3, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_3))))) = '1' then 
        if std_logic'(((sync_reset AND full_3) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_4))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_3 <= std_logic'('0');
        else
          stage_3 <= p3_stage_3;
        end if;
      end if;
    end if;

  end process;

  --control_3, which is an e_mux
  p3_full_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_2, full_4);
  --control_reg_3, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_3 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_3 <= std_logic'('0');
        else
          full_3 <= p3_full_3;
        end if;
      end if;
    end if;

  end process;

  --data_2, which is an e_mux
  p2_stage_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_3 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_3);
  --data_reg_2, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_2))))) = '1' then 
        if std_logic'(((sync_reset AND full_2) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_2 <= std_logic'('0');
        else
          stage_2 <= p2_stage_2;
        end if;
      end if;
    end if;

  end process;

  --control_2, which is an e_mux
  p2_full_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_1, full_3);
  --control_reg_2, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_2 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_2 <= std_logic'('0');
        else
          full_2 <= p2_full_2;
        end if;
      end if;
    end if;

  end process;

  --data_1, which is an e_mux
  p1_stage_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_2);
  --data_reg_1, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then 
        if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_1 <= std_logic'('0');
        else
          stage_1 <= p1_stage_1;
        end if;
      end if;
    end if;

  end process;

  --control_1, which is an e_mux
  p1_full_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_0, full_2);
  --control_reg_1, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(clear_fifo) = '1' then 
          full_1 <= std_logic'('0');
        else
          full_1 <= p1_full_1;
        end if;
      end if;
    end if;

  end process;

  --data_0, which is an e_mux
  p0_stage_0 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
  --data_reg_0, which is an e_register
  process (clk)
  begin
    if clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then 
          stage_0 <= std_logic'('0');
        else
          stage_0 <= p0_stage_0;
        end if;
      end if;
    end if;

  end process;

  --control_0, which is an e_mux
  p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
  --control_reg_0, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      full_0 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then 
        if std_logic'((clear_fifo AND NOT write)) = '1' then 
          full_0 <= std_logic'('0');
        else
          full_0 <= p0_full_0;
        end if;
      end if;
    end if;

  end process;

  one_count_plus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 4);
  one_count_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 4);
  --updated_one_count, which is an e_mux
  updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(data_in))), A_WE_StdLogicVector((std_logic'(((((read AND (data_in)) AND write) AND (stage_0)))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (data_in)))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (stage_0)))) = '1'), one_count_minus_one, how_many_ones))))))), 4);
  --counts how many ones in the data pipeline, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      how_many_ones <= std_logic_vector'("0000");
    elsif clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then 
        how_many_ones <= updated_one_count;
      end if;
    end if;

  end process;

  --this fifo contains ones in the data pipeline, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_contains_ones_n <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then 
        fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity SDRAM_s1_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_data_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal CPU_data_master_no_byte_enables_and_last_term : IN STD_LOGIC;
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_instruction_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                 signal CPU_instruction_master_read : IN STD_LOGIC;
                 signal SDRAM_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal SDRAM_s1_readdatavalid : IN STD_LOGIC;
                 signal SDRAM_s1_waitrequest : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_byteenable_SDRAM_s1 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal CPU_data_master_granted_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SDRAM_s1_shift_register : OUT STD_LOGIC;
                 signal CPU_data_master_requests_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_instruction_master_granted_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_instruction_master_qualified_request_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1 : OUT STD_LOGIC;
                 signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : OUT STD_LOGIC;
                 signal CPU_instruction_master_requests_SDRAM_s1 : OUT STD_LOGIC;
                 signal SDRAM_s1_address : OUT STD_LOGIC_VECTOR (21 DOWNTO 0);
                 signal SDRAM_s1_byteenable_n : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal SDRAM_s1_chipselect : OUT STD_LOGIC;
                 signal SDRAM_s1_read_n : OUT STD_LOGIC;
                 signal SDRAM_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal SDRAM_s1_reset_n : OUT STD_LOGIC;
                 signal SDRAM_s1_waitrequest_from_sa : OUT STD_LOGIC;
                 signal SDRAM_s1_write_n : OUT STD_LOGIC;
                 signal SDRAM_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_SDRAM_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of SDRAM_s1_arbitrator : entity is FALSE;
end entity SDRAM_s1_arbitrator;


architecture europa of SDRAM_s1_arbitrator is
component rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module is 
           port (
                 -- inputs:
                    signal clear_fifo : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal sync_reset : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC;
                    signal empty : OUT STD_LOGIC;
                    signal fifo_contains_ones_n : OUT STD_LOGIC;
                    signal full : OUT STD_LOGIC
                 );
end component rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module;

component rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module is 
           port (
                 -- inputs:
                    signal clear_fifo : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal sync_reset : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC;
                    signal empty : OUT STD_LOGIC;
                    signal fifo_contains_ones_n : OUT STD_LOGIC;
                    signal full : OUT STD_LOGIC
                 );
end component rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module;

                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_byteenable_SDRAM_s1_segment_0 :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_data_master_byteenable_SDRAM_s1_segment_1 :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_rdv_fifo_empty_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_rdv_fifo_output_from_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_saved_grant_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock :  STD_LOGIC;
                signal CPU_instruction_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_instruction_master_continuerequest :  STD_LOGIC;
                signal CPU_instruction_master_rdv_fifo_empty_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_rdv_fifo_output_from_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_saved_grant_SDRAM_s1 :  STD_LOGIC;
                signal SDRAM_s1_allgrants :  STD_LOGIC;
                signal SDRAM_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal SDRAM_s1_any_continuerequest :  STD_LOGIC;
                signal SDRAM_s1_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_arb_counter_enable :  STD_LOGIC;
                signal SDRAM_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_arbitration_holdoff_internal :  STD_LOGIC;
                signal SDRAM_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal SDRAM_s1_begins_xfer :  STD_LOGIC;
                signal SDRAM_s1_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal SDRAM_s1_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_end_xfer :  STD_LOGIC;
                signal SDRAM_s1_firsttransfer :  STD_LOGIC;
                signal SDRAM_s1_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_in_a_read_cycle :  STD_LOGIC;
                signal SDRAM_s1_in_a_write_cycle :  STD_LOGIC;
                signal SDRAM_s1_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_move_on_to_next_transaction :  STD_LOGIC;
                signal SDRAM_s1_non_bursting_master_requests :  STD_LOGIC;
                signal SDRAM_s1_readdatavalid_from_sa :  STD_LOGIC;
                signal SDRAM_s1_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_slavearbiterlockenable :  STD_LOGIC;
                signal SDRAM_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal SDRAM_s1_waits_for_read :  STD_LOGIC;
                signal SDRAM_s1_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_byteenable_SDRAM_s1 :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_CPU_data_master_granted_SDRAM_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_SDRAM_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_read_data_valid_SDRAM_s1_shift_register :  STD_LOGIC;
                signal internal_CPU_data_master_requests_SDRAM_s1 :  STD_LOGIC;
                signal internal_CPU_instruction_master_granted_SDRAM_s1 :  STD_LOGIC;
                signal internal_CPU_instruction_master_qualified_request_SDRAM_s1 :  STD_LOGIC;
                signal internal_CPU_instruction_master_requests_SDRAM_s1 :  STD_LOGIC;
                signal internal_SDRAM_s1_waitrequest_from_sa :  STD_LOGIC;
                signal last_cycle_CPU_data_master_granted_slave_SDRAM_s1 :  STD_LOGIC;
                signal last_cycle_CPU_instruction_master_granted_slave_SDRAM_s1 :  STD_LOGIC;
                signal module_input1 :  STD_LOGIC;
                signal module_input2 :  STD_LOGIC;
                signal module_input3 :  STD_LOGIC;
                signal module_input4 :  STD_LOGIC;
                signal module_input5 :  STD_LOGIC;
                signal module_input6 :  STD_LOGIC;
                signal wait_for_SDRAM_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT SDRAM_s1_end_xfer;
      end if;
    end if;

  end process;

  SDRAM_s1_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_CPU_data_master_qualified_request_SDRAM_s1 OR internal_CPU_instruction_master_qualified_request_SDRAM_s1));
  --assign SDRAM_s1_readdatavalid_from_sa = SDRAM_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  SDRAM_s1_readdatavalid_from_sa <= SDRAM_s1_readdatavalid;
  --assign SDRAM_s1_readdata_from_sa = SDRAM_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  SDRAM_s1_readdata_from_sa <= SDRAM_s1_readdata;
  internal_CPU_data_master_requests_SDRAM_s1 <= to_std_logic(((Std_Logic_Vector'(A_ToStdLogicVector(CPU_data_master_address_to_slave(23)) & std_logic_vector'("00000000000000000000000")) = std_logic_vector'("000000000000000000000000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign SDRAM_s1_waitrequest_from_sa = SDRAM_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_SDRAM_s1_waitrequest_from_sa <= SDRAM_s1_waitrequest;
  --SDRAM_s1_arb_share_counter set values, which is an e_mux
  SDRAM_s1_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((internal_CPU_instruction_master_granted_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((internal_CPU_instruction_master_granted_SDRAM_s1)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001"))))), 2);
  --SDRAM_s1_non_bursting_master_requests mux, which is an e_mux
  SDRAM_s1_non_bursting_master_requests <= ((internal_CPU_data_master_requests_SDRAM_s1 OR internal_CPU_instruction_master_requests_SDRAM_s1) OR internal_CPU_data_master_requests_SDRAM_s1) OR internal_CPU_instruction_master_requests_SDRAM_s1;
  --SDRAM_s1_arb_share_counter_next_value assignment, which is an e_assign
  SDRAM_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(SDRAM_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (SDRAM_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(SDRAM_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (SDRAM_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --SDRAM_s1_allgrants all slave grants, which is an e_mux
  SDRAM_s1_allgrants <= ((or_reduce(SDRAM_s1_grant_vector) OR or_reduce(SDRAM_s1_grant_vector)) OR or_reduce(SDRAM_s1_grant_vector)) OR or_reduce(SDRAM_s1_grant_vector);
  --SDRAM_s1_end_xfer assignment, which is an e_assign
  SDRAM_s1_end_xfer <= NOT ((SDRAM_s1_waits_for_read OR SDRAM_s1_waits_for_write));
  --SDRAM_s1_arb_share_counter arbitration counter enable, which is an e_assign
  SDRAM_s1_arb_counter_enable <= ((SDRAM_s1_end_xfer AND SDRAM_s1_allgrants)) OR ((SDRAM_s1_end_xfer AND NOT SDRAM_s1_non_bursting_master_requests));
  --SDRAM_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SDRAM_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(SDRAM_s1_arb_counter_enable) = '1' then 
        SDRAM_s1_arb_share_counter <= SDRAM_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --SDRAM_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SDRAM_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((or_reduce(SDRAM_s1_master_qreq_vector) AND SDRAM_s1_end_xfer)) OR ((SDRAM_s1_end_xfer AND NOT SDRAM_s1_non_bursting_master_requests)))) = '1' then 
        SDRAM_s1_slavearbiterlockenable <= or_reduce(SDRAM_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master SDRAM/s1 arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= SDRAM_s1_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --SDRAM_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  SDRAM_s1_slavearbiterlockenable2 <= or_reduce(SDRAM_s1_arb_share_counter_next_value);
  --CPU/data_master SDRAM/s1 arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= SDRAM_s1_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --CPU/instruction_master SDRAM/s1 arbiterlock, which is an e_assign
  CPU_instruction_master_arbiterlock <= SDRAM_s1_slavearbiterlockenable AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master SDRAM/s1 arbiterlock2, which is an e_assign
  CPU_instruction_master_arbiterlock2 <= SDRAM_s1_slavearbiterlockenable2 AND CPU_instruction_master_continuerequest;
  --CPU/instruction_master granted SDRAM/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_instruction_master_granted_slave_SDRAM_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_instruction_master_granted_slave_SDRAM_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_instruction_master_saved_grant_SDRAM_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((SDRAM_s1_arbitration_holdoff_internal OR NOT internal_CPU_instruction_master_requests_SDRAM_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_instruction_master_granted_slave_SDRAM_s1))))));
      end if;
    end if;

  end process;

  --CPU_instruction_master_continuerequest continued request, which is an e_mux
  CPU_instruction_master_continuerequest <= last_cycle_CPU_instruction_master_granted_slave_SDRAM_s1 AND internal_CPU_instruction_master_requests_SDRAM_s1;
  --SDRAM_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  SDRAM_s1_any_continuerequest <= CPU_instruction_master_continuerequest OR CPU_data_master_continuerequest;
  internal_CPU_data_master_qualified_request_SDRAM_s1 <= internal_CPU_data_master_requests_SDRAM_s1 AND NOT (((((CPU_data_master_read AND ((NOT CPU_data_master_waitrequest OR (internal_CPU_data_master_read_data_valid_SDRAM_s1_shift_register))))) OR (((((NOT CPU_data_master_waitrequest OR CPU_data_master_no_byte_enables_and_last_term) OR NOT(or_reduce(internal_CPU_data_master_byteenable_SDRAM_s1)))) AND CPU_data_master_write))) OR CPU_instruction_master_arbiterlock));
  --unique name for SDRAM_s1_move_on_to_next_transaction, which is an e_assign
  SDRAM_s1_move_on_to_next_transaction <= SDRAM_s1_readdatavalid_from_sa;
  --rdv_fifo_for_CPU_data_master_to_SDRAM_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_CPU_data_master_to_SDRAM_s1 : rdv_fifo_for_CPU_data_master_to_SDRAM_s1_module
    port map(
      data_out => CPU_data_master_rdv_fifo_output_from_SDRAM_s1,
      empty => open,
      fifo_contains_ones_n => CPU_data_master_rdv_fifo_empty_SDRAM_s1,
      full => open,
      clear_fifo => module_input1,
      clk => clk,
      data_in => internal_CPU_data_master_granted_SDRAM_s1,
      read => SDRAM_s1_move_on_to_next_transaction,
      reset_n => reset_n,
      sync_reset => module_input2,
      write => module_input3
    );

  module_input1 <= std_logic'('0');
  module_input2 <= std_logic'('0');
  module_input3 <= in_a_read_cycle AND NOT SDRAM_s1_waits_for_read;

  internal_CPU_data_master_read_data_valid_SDRAM_s1_shift_register <= NOT CPU_data_master_rdv_fifo_empty_SDRAM_s1;
  --local readdatavalid CPU_data_master_read_data_valid_SDRAM_s1, which is an e_mux
  CPU_data_master_read_data_valid_SDRAM_s1 <= ((SDRAM_s1_readdatavalid_from_sa AND CPU_data_master_rdv_fifo_output_from_SDRAM_s1)) AND NOT CPU_data_master_rdv_fifo_empty_SDRAM_s1;
  --SDRAM_s1_writedata mux, which is an e_mux
  SDRAM_s1_writedata <= CPU_data_master_dbs_write_16;
  internal_CPU_instruction_master_requests_SDRAM_s1 <= ((to_std_logic(((Std_Logic_Vector'(A_ToStdLogicVector(CPU_instruction_master_address_to_slave(23)) & std_logic_vector'("00000000000000000000000")) = std_logic_vector'("000000000000000000000000")))) AND (CPU_instruction_master_read))) AND CPU_instruction_master_read;
  --CPU/data_master granted SDRAM/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_CPU_data_master_granted_slave_SDRAM_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_CPU_data_master_granted_slave_SDRAM_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(CPU_data_master_saved_grant_SDRAM_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((SDRAM_s1_arbitration_holdoff_internal OR NOT internal_CPU_data_master_requests_SDRAM_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_CPU_data_master_granted_slave_SDRAM_s1))))));
      end if;
    end if;

  end process;

  --CPU_data_master_continuerequest continued request, which is an e_mux
  CPU_data_master_continuerequest <= last_cycle_CPU_data_master_granted_slave_SDRAM_s1 AND internal_CPU_data_master_requests_SDRAM_s1;
  internal_CPU_instruction_master_qualified_request_SDRAM_s1 <= internal_CPU_instruction_master_requests_SDRAM_s1 AND NOT ((((CPU_instruction_master_read AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000"))) OR ((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_latency_counter)))))))))) OR CPU_data_master_arbiterlock));
  --rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1 : rdv_fifo_for_CPU_instruction_master_to_SDRAM_s1_module
    port map(
      data_out => CPU_instruction_master_rdv_fifo_output_from_SDRAM_s1,
      empty => open,
      fifo_contains_ones_n => CPU_instruction_master_rdv_fifo_empty_SDRAM_s1,
      full => open,
      clear_fifo => module_input4,
      clk => clk,
      data_in => internal_CPU_instruction_master_granted_SDRAM_s1,
      read => SDRAM_s1_move_on_to_next_transaction,
      reset_n => reset_n,
      sync_reset => module_input5,
      write => module_input6
    );

  module_input4 <= std_logic'('0');
  module_input5 <= std_logic'('0');
  module_input6 <= in_a_read_cycle AND NOT SDRAM_s1_waits_for_read;

  CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register <= NOT CPU_instruction_master_rdv_fifo_empty_SDRAM_s1;
  --local readdatavalid CPU_instruction_master_read_data_valid_SDRAM_s1, which is an e_mux
  CPU_instruction_master_read_data_valid_SDRAM_s1 <= ((SDRAM_s1_readdatavalid_from_sa AND CPU_instruction_master_rdv_fifo_output_from_SDRAM_s1)) AND NOT CPU_instruction_master_rdv_fifo_empty_SDRAM_s1;
  --allow new arb cycle for SDRAM/s1, which is an e_assign
  SDRAM_s1_allow_new_arb_cycle <= NOT CPU_data_master_arbiterlock AND NOT CPU_instruction_master_arbiterlock;
  --CPU/instruction_master assignment into master qualified-requests vector for SDRAM/s1, which is an e_assign
  SDRAM_s1_master_qreq_vector(0) <= internal_CPU_instruction_master_qualified_request_SDRAM_s1;
  --CPU/instruction_master grant SDRAM/s1, which is an e_assign
  internal_CPU_instruction_master_granted_SDRAM_s1 <= SDRAM_s1_grant_vector(0);
  --CPU/instruction_master saved-grant SDRAM/s1, which is an e_assign
  CPU_instruction_master_saved_grant_SDRAM_s1 <= SDRAM_s1_arb_winner(0) AND internal_CPU_instruction_master_requests_SDRAM_s1;
  --CPU/data_master assignment into master qualified-requests vector for SDRAM/s1, which is an e_assign
  SDRAM_s1_master_qreq_vector(1) <= internal_CPU_data_master_qualified_request_SDRAM_s1;
  --CPU/data_master grant SDRAM/s1, which is an e_assign
  internal_CPU_data_master_granted_SDRAM_s1 <= SDRAM_s1_grant_vector(1);
  --CPU/data_master saved-grant SDRAM/s1, which is an e_assign
  CPU_data_master_saved_grant_SDRAM_s1 <= SDRAM_s1_arb_winner(1) AND internal_CPU_data_master_requests_SDRAM_s1;
  --SDRAM/s1 chosen-master double-vector, which is an e_assign
  SDRAM_s1_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((SDRAM_s1_master_qreq_vector & SDRAM_s1_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT SDRAM_s1_master_qreq_vector & NOT SDRAM_s1_master_qreq_vector))) + (std_logic_vector'("000") & (SDRAM_s1_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  SDRAM_s1_arb_winner <= A_WE_StdLogicVector((std_logic'(((SDRAM_s1_allow_new_arb_cycle AND or_reduce(SDRAM_s1_grant_vector)))) = '1'), SDRAM_s1_grant_vector, SDRAM_s1_saved_chosen_master_vector);
  --saved SDRAM_s1_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SDRAM_s1_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(SDRAM_s1_allow_new_arb_cycle) = '1' then 
        SDRAM_s1_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(SDRAM_s1_grant_vector)) = '1'), SDRAM_s1_grant_vector, SDRAM_s1_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  SDRAM_s1_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((SDRAM_s1_chosen_master_double_vector(1) OR SDRAM_s1_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((SDRAM_s1_chosen_master_double_vector(0) OR SDRAM_s1_chosen_master_double_vector(2)))));
  --SDRAM/s1 chosen master rotated left, which is an e_assign
  SDRAM_s1_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(SDRAM_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(SDRAM_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --SDRAM/s1's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SDRAM_s1_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(SDRAM_s1_grant_vector)) = '1' then 
        SDRAM_s1_arb_addend <= A_WE_StdLogicVector((std_logic'(SDRAM_s1_end_xfer) = '1'), SDRAM_s1_chosen_master_rot_left, SDRAM_s1_grant_vector);
      end if;
    end if;

  end process;

  --SDRAM_s1_reset_n assignment, which is an e_assign
  SDRAM_s1_reset_n <= reset_n;
  SDRAM_s1_chipselect <= internal_CPU_data_master_granted_SDRAM_s1 OR internal_CPU_instruction_master_granted_SDRAM_s1;
  --SDRAM_s1_firsttransfer first transaction, which is an e_assign
  SDRAM_s1_firsttransfer <= NOT ((SDRAM_s1_slavearbiterlockenable AND SDRAM_s1_any_continuerequest));
  --SDRAM_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  SDRAM_s1_beginbursttransfer_internal <= SDRAM_s1_begins_xfer AND SDRAM_s1_firsttransfer;
  --SDRAM_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  SDRAM_s1_arbitration_holdoff_internal <= SDRAM_s1_begins_xfer AND SDRAM_s1_firsttransfer;
  --~SDRAM_s1_read_n assignment, which is an e_mux
  SDRAM_s1_read_n <= NOT ((((internal_CPU_data_master_granted_SDRAM_s1 AND CPU_data_master_read)) OR ((internal_CPU_instruction_master_granted_SDRAM_s1 AND CPU_instruction_master_read))));
  --~SDRAM_s1_write_n assignment, which is an e_mux
  SDRAM_s1_write_n <= NOT ((internal_CPU_data_master_granted_SDRAM_s1 AND CPU_data_master_write));
  --SDRAM_s1_address mux, which is an e_mux
  SDRAM_s1_address <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_SDRAM_s1)) = '1'), (Std_Logic_Vector'(A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(CPU_data_master_dbs_address(1)))), (Std_Logic_Vector'(A_SRL(CPU_instruction_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(CPU_instruction_master_dbs_address(1))))), 22);
  --d1_SDRAM_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_SDRAM_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_SDRAM_s1_end_xfer <= SDRAM_s1_end_xfer;
      end if;
    end if;

  end process;

  --SDRAM_s1_waits_for_read in a cycle, which is an e_mux
  SDRAM_s1_waits_for_read <= SDRAM_s1_in_a_read_cycle AND internal_SDRAM_s1_waitrequest_from_sa;
  --SDRAM_s1_in_a_read_cycle assignment, which is an e_assign
  SDRAM_s1_in_a_read_cycle <= ((internal_CPU_data_master_granted_SDRAM_s1 AND CPU_data_master_read)) OR ((internal_CPU_instruction_master_granted_SDRAM_s1 AND CPU_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= SDRAM_s1_in_a_read_cycle;
  --SDRAM_s1_waits_for_write in a cycle, which is an e_mux
  SDRAM_s1_waits_for_write <= SDRAM_s1_in_a_write_cycle AND internal_SDRAM_s1_waitrequest_from_sa;
  --SDRAM_s1_in_a_write_cycle assignment, which is an e_assign
  SDRAM_s1_in_a_write_cycle <= internal_CPU_data_master_granted_SDRAM_s1 AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= SDRAM_s1_in_a_write_cycle;
  wait_for_SDRAM_s1_counter <= std_logic'('0');
  --~SDRAM_s1_byteenable_n byte enable port mux, which is an e_mux
  SDRAM_s1_byteenable_n <= A_EXT (NOT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_SDRAM_s1)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_CPU_data_master_byteenable_SDRAM_s1)), -SIGNED(std_logic_vector'("00000000000000000000000000000001")))), 2);
  (CPU_data_master_byteenable_SDRAM_s1_segment_1(1), CPU_data_master_byteenable_SDRAM_s1_segment_1(0), CPU_data_master_byteenable_SDRAM_s1_segment_0(1), CPU_data_master_byteenable_SDRAM_s1_segment_0(0)) <= CPU_data_master_byteenable;
  internal_CPU_data_master_byteenable_SDRAM_s1 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_data_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), CPU_data_master_byteenable_SDRAM_s1_segment_0, CPU_data_master_byteenable_SDRAM_s1_segment_1);
  --vhdl renameroo for output signals
  CPU_data_master_byteenable_SDRAM_s1 <= internal_CPU_data_master_byteenable_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_data_master_granted_SDRAM_s1 <= internal_CPU_data_master_granted_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_SDRAM_s1 <= internal_CPU_data_master_qualified_request_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_data_master_read_data_valid_SDRAM_s1_shift_register <= internal_CPU_data_master_read_data_valid_SDRAM_s1_shift_register;
  --vhdl renameroo for output signals
  CPU_data_master_requests_SDRAM_s1 <= internal_CPU_data_master_requests_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_instruction_master_granted_SDRAM_s1 <= internal_CPU_instruction_master_granted_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_instruction_master_qualified_request_SDRAM_s1 <= internal_CPU_instruction_master_qualified_request_SDRAM_s1;
  --vhdl renameroo for output signals
  CPU_instruction_master_requests_SDRAM_s1 <= internal_CPU_instruction_master_requests_SDRAM_s1;
  --vhdl renameroo for output signals
  SDRAM_s1_waitrequest_from_sa <= internal_SDRAM_s1_waitrequest_from_sa;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line6 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_data_master_granted_SDRAM_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_CPU_instruction_master_granted_SDRAM_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line6, now);
          write(write_line6, string'(": "));
          write(write_line6, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line6.all);
          deallocate (write_line6);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line7 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_data_master_saved_grant_SDRAM_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(CPU_instruction_master_saved_grant_SDRAM_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line7, now);
          write(write_line7, string'(": "));
          write(write_line7, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line7.all);
          deallocate (write_line7);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SWITCHES_s1_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal SWITCHES_s1_readdata : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_SWITCHES_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_SWITCHES_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_SWITCHES_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_requests_SWITCHES_s1 : OUT STD_LOGIC;
                 signal SWITCHES_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal SWITCHES_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal SWITCHES_s1_reset_n : OUT STD_LOGIC;
                 signal d1_SWITCHES_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of SWITCHES_s1_arbitrator : entity is FALSE;
end entity SWITCHES_s1_arbitrator;


architecture europa of SWITCHES_s1_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_SWITCHES_s1 :  STD_LOGIC;
                signal SWITCHES_s1_allgrants :  STD_LOGIC;
                signal SWITCHES_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal SWITCHES_s1_any_continuerequest :  STD_LOGIC;
                signal SWITCHES_s1_arb_counter_enable :  STD_LOGIC;
                signal SWITCHES_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SWITCHES_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SWITCHES_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SWITCHES_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal SWITCHES_s1_begins_xfer :  STD_LOGIC;
                signal SWITCHES_s1_end_xfer :  STD_LOGIC;
                signal SWITCHES_s1_firsttransfer :  STD_LOGIC;
                signal SWITCHES_s1_grant_vector :  STD_LOGIC;
                signal SWITCHES_s1_in_a_read_cycle :  STD_LOGIC;
                signal SWITCHES_s1_in_a_write_cycle :  STD_LOGIC;
                signal SWITCHES_s1_master_qreq_vector :  STD_LOGIC;
                signal SWITCHES_s1_non_bursting_master_requests :  STD_LOGIC;
                signal SWITCHES_s1_slavearbiterlockenable :  STD_LOGIC;
                signal SWITCHES_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal SWITCHES_s1_waits_for_read :  STD_LOGIC;
                signal SWITCHES_s1_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_SWITCHES_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_SWITCHES_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_requests_SWITCHES_s1 :  STD_LOGIC;
                signal wait_for_SWITCHES_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT SWITCHES_s1_end_xfer;
      end if;
    end if;

  end process;

  SWITCHES_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_SWITCHES_s1);
  --assign SWITCHES_s1_readdata_from_sa = SWITCHES_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  SWITCHES_s1_readdata_from_sa <= SWITCHES_s1_readdata;
  internal_CPU_data_master_requests_SWITCHES_s1 <= ((to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000001000100010000000")))) AND ((CPU_data_master_read OR CPU_data_master_write)))) AND CPU_data_master_read;
  --SWITCHES_s1_arb_share_counter set values, which is an e_mux
  SWITCHES_s1_arb_share_set_values <= std_logic_vector'("01");
  --SWITCHES_s1_non_bursting_master_requests mux, which is an e_mux
  SWITCHES_s1_non_bursting_master_requests <= internal_CPU_data_master_requests_SWITCHES_s1;
  --SWITCHES_s1_arb_share_counter_next_value assignment, which is an e_assign
  SWITCHES_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(SWITCHES_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (SWITCHES_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(SWITCHES_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (SWITCHES_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --SWITCHES_s1_allgrants all slave grants, which is an e_mux
  SWITCHES_s1_allgrants <= SWITCHES_s1_grant_vector;
  --SWITCHES_s1_end_xfer assignment, which is an e_assign
  SWITCHES_s1_end_xfer <= NOT ((SWITCHES_s1_waits_for_read OR SWITCHES_s1_waits_for_write));
  --SWITCHES_s1_arb_share_counter arbitration counter enable, which is an e_assign
  SWITCHES_s1_arb_counter_enable <= ((SWITCHES_s1_end_xfer AND SWITCHES_s1_allgrants)) OR ((SWITCHES_s1_end_xfer AND NOT SWITCHES_s1_non_bursting_master_requests));
  --SWITCHES_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SWITCHES_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(SWITCHES_s1_arb_counter_enable) = '1' then 
        SWITCHES_s1_arb_share_counter <= SWITCHES_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --SWITCHES_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      SWITCHES_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((SWITCHES_s1_master_qreq_vector AND SWITCHES_s1_end_xfer)) OR ((SWITCHES_s1_end_xfer AND NOT SWITCHES_s1_non_bursting_master_requests)))) = '1' then 
        SWITCHES_s1_slavearbiterlockenable <= or_reduce(SWITCHES_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master SWITCHES/s1 arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= SWITCHES_s1_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --SWITCHES_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  SWITCHES_s1_slavearbiterlockenable2 <= or_reduce(SWITCHES_s1_arb_share_counter_next_value);
  --CPU/data_master SWITCHES/s1 arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= SWITCHES_s1_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --SWITCHES_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  SWITCHES_s1_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_SWITCHES_s1 <= internal_CPU_data_master_requests_SWITCHES_s1;
  --master is always granted when requested
  internal_CPU_data_master_granted_SWITCHES_s1 <= internal_CPU_data_master_qualified_request_SWITCHES_s1;
  --CPU/data_master saved-grant SWITCHES/s1, which is an e_assign
  CPU_data_master_saved_grant_SWITCHES_s1 <= internal_CPU_data_master_requests_SWITCHES_s1;
  --allow new arb cycle for SWITCHES/s1, which is an e_assign
  SWITCHES_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  SWITCHES_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  SWITCHES_s1_master_qreq_vector <= std_logic'('1');
  --SWITCHES_s1_reset_n assignment, which is an e_assign
  SWITCHES_s1_reset_n <= reset_n;
  --SWITCHES_s1_firsttransfer first transaction, which is an e_assign
  SWITCHES_s1_firsttransfer <= NOT ((SWITCHES_s1_slavearbiterlockenable AND SWITCHES_s1_any_continuerequest));
  --SWITCHES_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  SWITCHES_s1_beginbursttransfer_internal <= SWITCHES_s1_begins_xfer AND SWITCHES_s1_firsttransfer;
  --SWITCHES_s1_address mux, which is an e_mux
  SWITCHES_s1_address <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_SWITCHES_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_SWITCHES_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_SWITCHES_s1_end_xfer <= SWITCHES_s1_end_xfer;
      end if;
    end if;

  end process;

  --SWITCHES_s1_waits_for_read in a cycle, which is an e_mux
  SWITCHES_s1_waits_for_read <= SWITCHES_s1_in_a_read_cycle AND SWITCHES_s1_begins_xfer;
  --SWITCHES_s1_in_a_read_cycle assignment, which is an e_assign
  SWITCHES_s1_in_a_read_cycle <= internal_CPU_data_master_granted_SWITCHES_s1 AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= SWITCHES_s1_in_a_read_cycle;
  --SWITCHES_s1_waits_for_write in a cycle, which is an e_mux
  SWITCHES_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(SWITCHES_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --SWITCHES_s1_in_a_write_cycle assignment, which is an e_assign
  SWITCHES_s1_in_a_write_cycle <= internal_CPU_data_master_granted_SWITCHES_s1 AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= SWITCHES_s1_in_a_write_cycle;
  wait_for_SWITCHES_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  CPU_data_master_granted_SWITCHES_s1 <= internal_CPU_data_master_granted_SWITCHES_s1;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_SWITCHES_s1 <= internal_CPU_data_master_qualified_request_SWITCHES_s1;
  --vhdl renameroo for output signals
  CPU_data_master_requests_SWITCHES_s1 <= internal_CPU_data_master_requests_SWITCHES_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity TIMER0_s1_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal TIMER0_s1_irq : IN STD_LOGIC;
                 signal TIMER0_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_TIMER0_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_TIMER0_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_TIMER0_s1 : OUT STD_LOGIC;
                 signal CPU_data_master_requests_TIMER0_s1 : OUT STD_LOGIC;
                 signal TIMER0_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal TIMER0_s1_chipselect : OUT STD_LOGIC;
                 signal TIMER0_s1_irq_from_sa : OUT STD_LOGIC;
                 signal TIMER0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal TIMER0_s1_reset_n : OUT STD_LOGIC;
                 signal TIMER0_s1_write_n : OUT STD_LOGIC;
                 signal TIMER0_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_TIMER0_s1_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of TIMER0_s1_arbitrator : entity is FALSE;
end entity TIMER0_s1_arbitrator;


architecture europa of TIMER0_s1_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_TIMER0_s1 :  STD_LOGIC;
                signal TIMER0_s1_allgrants :  STD_LOGIC;
                signal TIMER0_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal TIMER0_s1_any_continuerequest :  STD_LOGIC;
                signal TIMER0_s1_arb_counter_enable :  STD_LOGIC;
                signal TIMER0_s1_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal TIMER0_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal TIMER0_s1_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal TIMER0_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal TIMER0_s1_begins_xfer :  STD_LOGIC;
                signal TIMER0_s1_end_xfer :  STD_LOGIC;
                signal TIMER0_s1_firsttransfer :  STD_LOGIC;
                signal TIMER0_s1_grant_vector :  STD_LOGIC;
                signal TIMER0_s1_in_a_read_cycle :  STD_LOGIC;
                signal TIMER0_s1_in_a_write_cycle :  STD_LOGIC;
                signal TIMER0_s1_master_qreq_vector :  STD_LOGIC;
                signal TIMER0_s1_non_bursting_master_requests :  STD_LOGIC;
                signal TIMER0_s1_slavearbiterlockenable :  STD_LOGIC;
                signal TIMER0_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal TIMER0_s1_waits_for_read :  STD_LOGIC;
                signal TIMER0_s1_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_TIMER0_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_TIMER0_s1 :  STD_LOGIC;
                signal internal_CPU_data_master_requests_TIMER0_s1 :  STD_LOGIC;
                signal wait_for_TIMER0_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT TIMER0_s1_end_xfer;
      end if;
    end if;

  end process;

  TIMER0_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_TIMER0_s1);
  --assign TIMER0_s1_readdata_from_sa = TIMER0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  TIMER0_s1_readdata_from_sa <= TIMER0_s1_readdata;
  internal_CPU_data_master_requests_TIMER0_s1 <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 5) & std_logic_vector'("00000")) = std_logic_vector'("100000001000100000000000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --TIMER0_s1_arb_share_counter set values, which is an e_mux
  TIMER0_s1_arb_share_set_values <= std_logic_vector'("01");
  --TIMER0_s1_non_bursting_master_requests mux, which is an e_mux
  TIMER0_s1_non_bursting_master_requests <= internal_CPU_data_master_requests_TIMER0_s1;
  --TIMER0_s1_arb_share_counter_next_value assignment, which is an e_assign
  TIMER0_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(TIMER0_s1_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (TIMER0_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(TIMER0_s1_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (TIMER0_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --TIMER0_s1_allgrants all slave grants, which is an e_mux
  TIMER0_s1_allgrants <= TIMER0_s1_grant_vector;
  --TIMER0_s1_end_xfer assignment, which is an e_assign
  TIMER0_s1_end_xfer <= NOT ((TIMER0_s1_waits_for_read OR TIMER0_s1_waits_for_write));
  --TIMER0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  TIMER0_s1_arb_counter_enable <= ((TIMER0_s1_end_xfer AND TIMER0_s1_allgrants)) OR ((TIMER0_s1_end_xfer AND NOT TIMER0_s1_non_bursting_master_requests));
  --TIMER0_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      TIMER0_s1_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(TIMER0_s1_arb_counter_enable) = '1' then 
        TIMER0_s1_arb_share_counter <= TIMER0_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --TIMER0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      TIMER0_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((TIMER0_s1_master_qreq_vector AND TIMER0_s1_end_xfer)) OR ((TIMER0_s1_end_xfer AND NOT TIMER0_s1_non_bursting_master_requests)))) = '1' then 
        TIMER0_s1_slavearbiterlockenable <= or_reduce(TIMER0_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master TIMER0/s1 arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= TIMER0_s1_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --TIMER0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  TIMER0_s1_slavearbiterlockenable2 <= or_reduce(TIMER0_s1_arb_share_counter_next_value);
  --CPU/data_master TIMER0/s1 arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= TIMER0_s1_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --TIMER0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  TIMER0_s1_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_TIMER0_s1 <= internal_CPU_data_master_requests_TIMER0_s1 AND NOT (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write));
  --TIMER0_s1_writedata mux, which is an e_mux
  TIMER0_s1_writedata <= CPU_data_master_writedata (15 DOWNTO 0);
  --master is always granted when requested
  internal_CPU_data_master_granted_TIMER0_s1 <= internal_CPU_data_master_qualified_request_TIMER0_s1;
  --CPU/data_master saved-grant TIMER0/s1, which is an e_assign
  CPU_data_master_saved_grant_TIMER0_s1 <= internal_CPU_data_master_requests_TIMER0_s1;
  --allow new arb cycle for TIMER0/s1, which is an e_assign
  TIMER0_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  TIMER0_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  TIMER0_s1_master_qreq_vector <= std_logic'('1');
  --TIMER0_s1_reset_n assignment, which is an e_assign
  TIMER0_s1_reset_n <= reset_n;
  TIMER0_s1_chipselect <= internal_CPU_data_master_granted_TIMER0_s1;
  --TIMER0_s1_firsttransfer first transaction, which is an e_assign
  TIMER0_s1_firsttransfer <= NOT ((TIMER0_s1_slavearbiterlockenable AND TIMER0_s1_any_continuerequest));
  --TIMER0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  TIMER0_s1_beginbursttransfer_internal <= TIMER0_s1_begins_xfer AND TIMER0_s1_firsttransfer;
  --~TIMER0_s1_write_n assignment, which is an e_mux
  TIMER0_s1_write_n <= NOT ((internal_CPU_data_master_granted_TIMER0_s1 AND CPU_data_master_write));
  --TIMER0_s1_address mux, which is an e_mux
  TIMER0_s1_address <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 3);
  --d1_TIMER0_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_TIMER0_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_TIMER0_s1_end_xfer <= TIMER0_s1_end_xfer;
      end if;
    end if;

  end process;

  --TIMER0_s1_waits_for_read in a cycle, which is an e_mux
  TIMER0_s1_waits_for_read <= TIMER0_s1_in_a_read_cycle AND TIMER0_s1_begins_xfer;
  --TIMER0_s1_in_a_read_cycle assignment, which is an e_assign
  TIMER0_s1_in_a_read_cycle <= internal_CPU_data_master_granted_TIMER0_s1 AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= TIMER0_s1_in_a_read_cycle;
  --TIMER0_s1_waits_for_write in a cycle, which is an e_mux
  TIMER0_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(TIMER0_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --TIMER0_s1_in_a_write_cycle assignment, which is an e_assign
  TIMER0_s1_in_a_write_cycle <= internal_CPU_data_master_granted_TIMER0_s1 AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= TIMER0_s1_in_a_write_cycle;
  wait_for_TIMER0_s1_counter <= std_logic'('0');
  --assign TIMER0_s1_irq_from_sa = TIMER0_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  TIMER0_s1_irq_from_sa <= TIMER0_s1_irq;
  --vhdl renameroo for output signals
  CPU_data_master_granted_TIMER0_s1 <= internal_CPU_data_master_granted_TIMER0_s1;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_TIMER0_s1 <= internal_CPU_data_master_qualified_request_TIMER0_s1;
  --vhdl renameroo for output signals
  CPU_data_master_requests_TIMER0_s1 <= internal_CPU_data_master_requests_TIMER0_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity VGA_avalon_character_slave_arbitrator is 
        port (
              -- inputs:
                 signal VGA_avalon_character_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_0_out_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                 signal clock_0_out_read : IN STD_LOGIC;
                 signal clock_0_out_write : IN STD_LOGIC;
                 signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal VGA_avalon_character_slave_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                 signal VGA_avalon_character_slave_chipselect : OUT STD_LOGIC;
                 signal VGA_avalon_character_slave_read : OUT STD_LOGIC;
                 signal VGA_avalon_character_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal VGA_avalon_character_slave_write : OUT STD_LOGIC;
                 signal VGA_avalon_character_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clock_0_out_granted_VGA_avalon_character_slave : OUT STD_LOGIC;
                 signal clock_0_out_qualified_request_VGA_avalon_character_slave : OUT STD_LOGIC;
                 signal clock_0_out_read_data_valid_VGA_avalon_character_slave : OUT STD_LOGIC;
                 signal clock_0_out_requests_VGA_avalon_character_slave : OUT STD_LOGIC;
                 signal d1_VGA_avalon_character_slave_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of VGA_avalon_character_slave_arbitrator : entity is FALSE;
end entity VGA_avalon_character_slave_arbitrator;


architecture europa of VGA_avalon_character_slave_arbitrator is
                signal VGA_avalon_character_slave_allgrants :  STD_LOGIC;
                signal VGA_avalon_character_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal VGA_avalon_character_slave_any_continuerequest :  STD_LOGIC;
                signal VGA_avalon_character_slave_arb_counter_enable :  STD_LOGIC;
                signal VGA_avalon_character_slave_arb_share_counter :  STD_LOGIC;
                signal VGA_avalon_character_slave_arb_share_counter_next_value :  STD_LOGIC;
                signal VGA_avalon_character_slave_arb_share_set_values :  STD_LOGIC;
                signal VGA_avalon_character_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal VGA_avalon_character_slave_begins_xfer :  STD_LOGIC;
                signal VGA_avalon_character_slave_end_xfer :  STD_LOGIC;
                signal VGA_avalon_character_slave_firsttransfer :  STD_LOGIC;
                signal VGA_avalon_character_slave_grant_vector :  STD_LOGIC;
                signal VGA_avalon_character_slave_in_a_read_cycle :  STD_LOGIC;
                signal VGA_avalon_character_slave_in_a_write_cycle :  STD_LOGIC;
                signal VGA_avalon_character_slave_master_qreq_vector :  STD_LOGIC;
                signal VGA_avalon_character_slave_non_bursting_master_requests :  STD_LOGIC;
                signal VGA_avalon_character_slave_slavearbiterlockenable :  STD_LOGIC;
                signal VGA_avalon_character_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal VGA_avalon_character_slave_waits_for_read :  STD_LOGIC;
                signal VGA_avalon_character_slave_waits_for_write :  STD_LOGIC;
                signal clock_0_out_arbiterlock :  STD_LOGIC;
                signal clock_0_out_arbiterlock2 :  STD_LOGIC;
                signal clock_0_out_continuerequest :  STD_LOGIC;
                signal clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register_in :  STD_LOGIC;
                signal clock_0_out_saved_grant_VGA_avalon_character_slave :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_0_out_granted_VGA_avalon_character_slave :  STD_LOGIC;
                signal internal_clock_0_out_qualified_request_VGA_avalon_character_slave :  STD_LOGIC;
                signal internal_clock_0_out_requests_VGA_avalon_character_slave :  STD_LOGIC;
                signal p1_clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal wait_for_VGA_avalon_character_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT VGA_avalon_character_slave_end_xfer;
      end if;
    end if;

  end process;

  VGA_avalon_character_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_0_out_qualified_request_VGA_avalon_character_slave);
  --assign VGA_avalon_character_slave_readdata_from_sa = VGA_avalon_character_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  VGA_avalon_character_slave_readdata_from_sa <= VGA_avalon_character_slave_readdata;
  internal_clock_0_out_requests_VGA_avalon_character_slave <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_0_out_read OR clock_0_out_write)))))));
  --VGA_avalon_character_slave_arb_share_counter set values, which is an e_mux
  VGA_avalon_character_slave_arb_share_set_values <= std_logic'('1');
  --VGA_avalon_character_slave_non_bursting_master_requests mux, which is an e_mux
  VGA_avalon_character_slave_non_bursting_master_requests <= internal_clock_0_out_requests_VGA_avalon_character_slave;
  --VGA_avalon_character_slave_arb_share_counter_next_value assignment, which is an e_assign
  VGA_avalon_character_slave_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(VGA_avalon_character_slave_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(VGA_avalon_character_slave_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(VGA_avalon_character_slave_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(VGA_avalon_character_slave_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --VGA_avalon_character_slave_allgrants all slave grants, which is an e_mux
  VGA_avalon_character_slave_allgrants <= VGA_avalon_character_slave_grant_vector;
  --VGA_avalon_character_slave_end_xfer assignment, which is an e_assign
  VGA_avalon_character_slave_end_xfer <= NOT ((VGA_avalon_character_slave_waits_for_read OR VGA_avalon_character_slave_waits_for_write));
  --VGA_avalon_character_slave_arb_share_counter arbitration counter enable, which is an e_assign
  VGA_avalon_character_slave_arb_counter_enable <= ((VGA_avalon_character_slave_end_xfer AND VGA_avalon_character_slave_allgrants)) OR ((VGA_avalon_character_slave_end_xfer AND NOT VGA_avalon_character_slave_non_bursting_master_requests));
  --VGA_avalon_character_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      VGA_avalon_character_slave_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(VGA_avalon_character_slave_arb_counter_enable) = '1' then 
        VGA_avalon_character_slave_arb_share_counter <= VGA_avalon_character_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --VGA_avalon_character_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      VGA_avalon_character_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((VGA_avalon_character_slave_master_qreq_vector AND VGA_avalon_character_slave_end_xfer)) OR ((VGA_avalon_character_slave_end_xfer AND NOT VGA_avalon_character_slave_non_bursting_master_requests)))) = '1' then 
        VGA_avalon_character_slave_slavearbiterlockenable <= VGA_avalon_character_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_0/out VGA/avalon_character_slave arbiterlock, which is an e_assign
  clock_0_out_arbiterlock <= VGA_avalon_character_slave_slavearbiterlockenable AND clock_0_out_continuerequest;
  --VGA_avalon_character_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  VGA_avalon_character_slave_slavearbiterlockenable2 <= VGA_avalon_character_slave_arb_share_counter_next_value;
  --clock_0/out VGA/avalon_character_slave arbiterlock2, which is an e_assign
  clock_0_out_arbiterlock2 <= VGA_avalon_character_slave_slavearbiterlockenable2 AND clock_0_out_continuerequest;
  --VGA_avalon_character_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  VGA_avalon_character_slave_any_continuerequest <= std_logic'('1');
  --clock_0_out_continuerequest continued request, which is an e_assign
  clock_0_out_continuerequest <= std_logic'('1');
  internal_clock_0_out_qualified_request_VGA_avalon_character_slave <= internal_clock_0_out_requests_VGA_avalon_character_slave AND NOT ((clock_0_out_read AND (or_reduce(clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register))));
  --clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register_in <= ((internal_clock_0_out_granted_VGA_avalon_character_slave AND clock_0_out_read) AND NOT VGA_avalon_character_slave_waits_for_read) AND NOT (or_reduce(clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register));
  --shift register p1 clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register <= A_EXT ((clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register & A_ToStdLogicVector(clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register_in)), 4);
  --clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register <= std_logic_vector'("0000");
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register <= p1_clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid clock_0_out_read_data_valid_VGA_avalon_character_slave, which is an e_mux
  clock_0_out_read_data_valid_VGA_avalon_character_slave <= clock_0_out_read_data_valid_VGA_avalon_character_slave_shift_register(3);
  --VGA_avalon_character_slave_writedata mux, which is an e_mux
  VGA_avalon_character_slave_writedata <= clock_0_out_writedata;
  --master is always granted when requested
  internal_clock_0_out_granted_VGA_avalon_character_slave <= internal_clock_0_out_qualified_request_VGA_avalon_character_slave;
  --clock_0/out saved-grant VGA/avalon_character_slave, which is an e_assign
  clock_0_out_saved_grant_VGA_avalon_character_slave <= internal_clock_0_out_requests_VGA_avalon_character_slave;
  --allow new arb cycle for VGA/avalon_character_slave, which is an e_assign
  VGA_avalon_character_slave_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  VGA_avalon_character_slave_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  VGA_avalon_character_slave_master_qreq_vector <= std_logic'('1');
  VGA_avalon_character_slave_chipselect <= internal_clock_0_out_granted_VGA_avalon_character_slave;
  --VGA_avalon_character_slave_firsttransfer first transaction, which is an e_assign
  VGA_avalon_character_slave_firsttransfer <= NOT ((VGA_avalon_character_slave_slavearbiterlockenable AND VGA_avalon_character_slave_any_continuerequest));
  --VGA_avalon_character_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  VGA_avalon_character_slave_beginbursttransfer_internal <= VGA_avalon_character_slave_begins_xfer AND VGA_avalon_character_slave_firsttransfer;
  --VGA_avalon_character_slave_read assignment, which is an e_mux
  VGA_avalon_character_slave_read <= internal_clock_0_out_granted_VGA_avalon_character_slave AND clock_0_out_read;
  --VGA_avalon_character_slave_write assignment, which is an e_mux
  VGA_avalon_character_slave_write <= internal_clock_0_out_granted_VGA_avalon_character_slave AND clock_0_out_write;
  --VGA_avalon_character_slave_address mux, which is an e_mux
  VGA_avalon_character_slave_address <= A_EXT (A_SRL(clock_0_out_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 13);
  --d1_VGA_avalon_character_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_VGA_avalon_character_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_VGA_avalon_character_slave_end_xfer <= VGA_avalon_character_slave_end_xfer;
      end if;
    end if;

  end process;

  --VGA_avalon_character_slave_waits_for_read in a cycle, which is an e_mux
  VGA_avalon_character_slave_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(VGA_avalon_character_slave_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --VGA_avalon_character_slave_in_a_read_cycle assignment, which is an e_assign
  VGA_avalon_character_slave_in_a_read_cycle <= internal_clock_0_out_granted_VGA_avalon_character_slave AND clock_0_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= VGA_avalon_character_slave_in_a_read_cycle;
  --VGA_avalon_character_slave_waits_for_write in a cycle, which is an e_mux
  VGA_avalon_character_slave_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(VGA_avalon_character_slave_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --VGA_avalon_character_slave_in_a_write_cycle assignment, which is an e_assign
  VGA_avalon_character_slave_in_a_write_cycle <= internal_clock_0_out_granted_VGA_avalon_character_slave AND clock_0_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= VGA_avalon_character_slave_in_a_write_cycle;
  wait_for_VGA_avalon_character_slave_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_0_out_granted_VGA_avalon_character_slave <= internal_clock_0_out_granted_VGA_avalon_character_slave;
  --vhdl renameroo for output signals
  clock_0_out_qualified_request_VGA_avalon_character_slave <= internal_clock_0_out_qualified_request_VGA_avalon_character_slave;
  --vhdl renameroo for output signals
  clock_0_out_requests_VGA_avalon_character_slave <= internal_clock_0_out_requests_VGA_avalon_character_slave;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity NIOS_II_reset_clk_25_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity NIOS_II_reset_clk_25_domain_synch_module;


architecture europa of NIOS_II_reset_clk_25_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_0_in_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_0_in_endofpacket : IN STD_LOGIC;
                 signal clock_0_in_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clock_0_in_waitrequest : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_clock_0_in : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_clock_0_in : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_clock_0_in : OUT STD_LOGIC;
                 signal CPU_data_master_requests_clock_0_in : OUT STD_LOGIC;
                 signal clock_0_in_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
                 signal clock_0_in_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clock_0_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_0_in_nativeaddress : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                 signal clock_0_in_read : OUT STD_LOGIC;
                 signal clock_0_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clock_0_in_reset_n : OUT STD_LOGIC;
                 signal clock_0_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_0_in_write : OUT STD_LOGIC;
                 signal clock_0_in_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_clock_0_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_0_in_arbitrator : entity is FALSE;
end entity clock_0_in_arbitrator;


architecture europa of clock_0_in_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_clock_0_in :  STD_LOGIC;
                signal clock_0_in_allgrants :  STD_LOGIC;
                signal clock_0_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_0_in_any_continuerequest :  STD_LOGIC;
                signal clock_0_in_arb_counter_enable :  STD_LOGIC;
                signal clock_0_in_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_in_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_in_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_0_in_begins_xfer :  STD_LOGIC;
                signal clock_0_in_end_xfer :  STD_LOGIC;
                signal clock_0_in_firsttransfer :  STD_LOGIC;
                signal clock_0_in_grant_vector :  STD_LOGIC;
                signal clock_0_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_0_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_0_in_master_qreq_vector :  STD_LOGIC;
                signal clock_0_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_0_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_0_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_0_in_waits_for_read :  STD_LOGIC;
                signal clock_0_in_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_clock_0_in :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_clock_0_in :  STD_LOGIC;
                signal internal_CPU_data_master_requests_clock_0_in :  STD_LOGIC;
                signal internal_clock_0_in_waitrequest_from_sa :  STD_LOGIC;
                signal wait_for_clock_0_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_0_in_end_xfer;
      end if;
    end if;

  end process;

  clock_0_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_clock_0_in);
  --assign clock_0_in_readdata_from_sa = clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_0_in_readdata_from_sa <= clock_0_in_readdata;
  internal_CPU_data_master_requests_clock_0_in <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 15) & std_logic_vector'("000000000000000")) = std_logic_vector'("100000000000000000000000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign clock_0_in_waitrequest_from_sa = clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_0_in_waitrequest_from_sa <= clock_0_in_waitrequest;
  --clock_0_in_arb_share_counter set values, which is an e_mux
  clock_0_in_arb_share_set_values <= std_logic_vector'("01");
  --clock_0_in_non_bursting_master_requests mux, which is an e_mux
  clock_0_in_non_bursting_master_requests <= internal_CPU_data_master_requests_clock_0_in;
  --clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_0_in_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(clock_0_in_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (clock_0_in_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(clock_0_in_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (clock_0_in_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --clock_0_in_allgrants all slave grants, which is an e_mux
  clock_0_in_allgrants <= clock_0_in_grant_vector;
  --clock_0_in_end_xfer assignment, which is an e_assign
  clock_0_in_end_xfer <= NOT ((clock_0_in_waits_for_read OR clock_0_in_waits_for_write));
  --clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_0_in_arb_counter_enable <= ((clock_0_in_end_xfer AND clock_0_in_allgrants)) OR ((clock_0_in_end_xfer AND NOT clock_0_in_non_bursting_master_requests));
  --clock_0_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_0_in_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(clock_0_in_arb_counter_enable) = '1' then 
        clock_0_in_arb_share_counter <= clock_0_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_0_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_0_in_master_qreq_vector AND clock_0_in_end_xfer)) OR ((clock_0_in_end_xfer AND NOT clock_0_in_non_bursting_master_requests)))) = '1' then 
        clock_0_in_slavearbiterlockenable <= or_reduce(clock_0_in_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master clock_0/in arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= clock_0_in_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_0_in_slavearbiterlockenable2 <= or_reduce(clock_0_in_arb_share_counter_next_value);
  --CPU/data_master clock_0/in arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= clock_0_in_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_0_in_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_clock_0_in <= internal_CPU_data_master_requests_clock_0_in AND NOT ((((CPU_data_master_read AND (NOT CPU_data_master_waitrequest))) OR (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write))));
  --clock_0_in_writedata mux, which is an e_mux
  clock_0_in_writedata <= CPU_data_master_writedata;
  --assign clock_0_in_endofpacket_from_sa = clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_0_in_endofpacket_from_sa <= clock_0_in_endofpacket;
  --master is always granted when requested
  internal_CPU_data_master_granted_clock_0_in <= internal_CPU_data_master_qualified_request_clock_0_in;
  --CPU/data_master saved-grant clock_0/in, which is an e_assign
  CPU_data_master_saved_grant_clock_0_in <= internal_CPU_data_master_requests_clock_0_in;
  --allow new arb cycle for clock_0/in, which is an e_assign
  clock_0_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_0_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_0_in_master_qreq_vector <= std_logic'('1');
  --clock_0_in_reset_n assignment, which is an e_assign
  clock_0_in_reset_n <= reset_n;
  --clock_0_in_firsttransfer first transaction, which is an e_assign
  clock_0_in_firsttransfer <= NOT ((clock_0_in_slavearbiterlockenable AND clock_0_in_any_continuerequest));
  --clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_0_in_beginbursttransfer_internal <= clock_0_in_begins_xfer AND clock_0_in_firsttransfer;
  --clock_0_in_read assignment, which is an e_mux
  clock_0_in_read <= internal_CPU_data_master_granted_clock_0_in AND CPU_data_master_read;
  --clock_0_in_write assignment, which is an e_mux
  clock_0_in_write <= internal_CPU_data_master_granted_clock_0_in AND CPU_data_master_write;
  --clock_0_in_address mux, which is an e_mux
  clock_0_in_address <= CPU_data_master_address_to_slave (14 DOWNTO 0);
  --slaveid clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_0_in_nativeaddress <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 13);
  --d1_clock_0_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_0_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_0_in_end_xfer <= clock_0_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_0_in_waits_for_read in a cycle, which is an e_mux
  clock_0_in_waits_for_read <= clock_0_in_in_a_read_cycle AND internal_clock_0_in_waitrequest_from_sa;
  --clock_0_in_in_a_read_cycle assignment, which is an e_assign
  clock_0_in_in_a_read_cycle <= internal_CPU_data_master_granted_clock_0_in AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_0_in_in_a_read_cycle;
  --clock_0_in_waits_for_write in a cycle, which is an e_mux
  clock_0_in_waits_for_write <= clock_0_in_in_a_write_cycle AND internal_clock_0_in_waitrequest_from_sa;
  --clock_0_in_in_a_write_cycle assignment, which is an e_assign
  clock_0_in_in_a_write_cycle <= internal_CPU_data_master_granted_clock_0_in AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_0_in_in_a_write_cycle;
  wait_for_clock_0_in_counter <= std_logic'('0');
  --clock_0_in_byteenable byte enable port mux, which is an e_mux
  clock_0_in_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_clock_0_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (CPU_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --vhdl renameroo for output signals
  CPU_data_master_granted_clock_0_in <= internal_CPU_data_master_granted_clock_0_in;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_clock_0_in <= internal_CPU_data_master_qualified_request_clock_0_in;
  --vhdl renameroo for output signals
  CPU_data_master_requests_clock_0_in <= internal_CPU_data_master_requests_clock_0_in;
  --vhdl renameroo for output signals
  clock_0_in_waitrequest_from_sa <= internal_clock_0_in_waitrequest_from_sa;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_0_out_arbitrator is 
        port (
              -- inputs:
                 signal VGA_avalon_character_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_0_out_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                 signal clock_0_out_granted_VGA_avalon_character_slave : IN STD_LOGIC;
                 signal clock_0_out_qualified_request_VGA_avalon_character_slave : IN STD_LOGIC;
                 signal clock_0_out_read : IN STD_LOGIC;
                 signal clock_0_out_read_data_valid_VGA_avalon_character_slave : IN STD_LOGIC;
                 signal clock_0_out_requests_VGA_avalon_character_slave : IN STD_LOGIC;
                 signal clock_0_out_write : IN STD_LOGIC;
                 signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_VGA_avalon_character_slave_end_xfer : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_0_out_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
                 signal clock_0_out_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clock_0_out_reset_n : OUT STD_LOGIC;
                 signal clock_0_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_0_out_arbitrator : entity is FALSE;
end entity clock_0_out_arbitrator;


architecture europa of clock_0_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_0_out_address_last_time :  STD_LOGIC_VECTOR (14 DOWNTO 0);
                signal clock_0_out_read_last_time :  STD_LOGIC;
                signal clock_0_out_run :  STD_LOGIC;
                signal clock_0_out_write_last_time :  STD_LOGIC;
                signal clock_0_out_writedata_last_time :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal internal_clock_0_out_address_to_slave :  STD_LOGIC_VECTOR (14 DOWNTO 0);
                signal internal_clock_0_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((clock_0_out_qualified_request_VGA_avalon_character_slave OR clock_0_out_read_data_valid_VGA_avalon_character_slave) OR NOT clock_0_out_requests_VGA_avalon_character_slave)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT clock_0_out_qualified_request_VGA_avalon_character_slave OR NOT clock_0_out_read) OR ((clock_0_out_read_data_valid_VGA_avalon_character_slave AND clock_0_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_0_out_qualified_request_VGA_avalon_character_slave OR NOT ((clock_0_out_read OR clock_0_out_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_0_out_read OR clock_0_out_write)))))))))));
  --cascaded wait assignment, which is an e_assign
  clock_0_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_0_out_address_to_slave <= clock_0_out_address;
  --clock_0/out readdata mux, which is an e_mux
  clock_0_out_readdata <= VGA_avalon_character_slave_readdata_from_sa;
  --actual waitrequest port, which is an e_assign
  internal_clock_0_out_waitrequest <= NOT clock_0_out_run;
  --clock_0_out_reset_n assignment, which is an e_assign
  clock_0_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_0_out_address_to_slave <= internal_clock_0_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_0_out_waitrequest <= internal_clock_0_out_waitrequest;
--synthesis translate_off
    --clock_0_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_address_last_time <= std_logic_vector'("000000000000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_address_last_time <= clock_0_out_address;
        end if;
      end if;

    end process;

    --clock_0/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_0_out_waitrequest AND ((clock_0_out_read OR clock_0_out_write));
        end if;
      end if;

    end process;

    --clock_0_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_address, clock_0_out_address_last_time)
    VARIABLE write_line8 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_0_out_address /= clock_0_out_address_last_time))))) = '1' then 
          write(write_line8, now);
          write(write_line8, string'(": "));
          write(write_line8, string'("clock_0_out_address did not heed wait!!!"));
          write(output, write_line8.all);
          deallocate (write_line8);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_read_last_time <= clock_0_out_read;
        end if;
      end if;

    end process;

    --clock_0_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_read, clock_0_out_read_last_time)
    VARIABLE write_line9 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_0_out_read) /= std_logic'(clock_0_out_read_last_time)))))) = '1' then 
          write(write_line9, now);
          write(write_line9, string'(": "));
          write(write_line9, string'("clock_0_out_read did not heed wait!!!"));
          write(output, write_line9.all);
          deallocate (write_line9);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_write_last_time <= clock_0_out_write;
        end if;
      end if;

    end process;

    --clock_0_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_write, clock_0_out_write_last_time)
    VARIABLE write_line10 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_0_out_write) /= std_logic'(clock_0_out_write_last_time)))))) = '1' then 
          write(write_line10, now);
          write(write_line10, string'(": "));
          write(write_line10, string'("clock_0_out_write did not heed wait!!!"));
          write(output, write_line10.all);
          deallocate (write_line10);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_writedata_last_time <= std_logic_vector'("00000000000000000000000000000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_writedata_last_time <= clock_0_out_writedata;
        end if;
      end if;

    end process;

    --clock_0_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_write, clock_0_out_writedata, clock_0_out_writedata_last_time)
    VARIABLE write_line11 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_0_out_writedata /= clock_0_out_writedata_last_time)))) AND clock_0_out_write)) = '1' then 
          write(write_line11, now);
          write(write_line11, string'(": "));
          write(write_line11, string'("clock_0_out_writedata did not heed wait!!!"));
          write(output, write_line11.all);
          deallocate (write_line11);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_1_in_arbitrator is 
        port (
              -- inputs:
                 signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal CPU_data_master_read : IN STD_LOGIC;
                 signal CPU_data_master_waitrequest : IN STD_LOGIC;
                 signal CPU_data_master_write : IN STD_LOGIC;
                 signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_1_in_endofpacket : IN STD_LOGIC;
                 signal clock_1_in_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clock_1_in_waitrequest : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal CPU_data_master_granted_clock_1_in : OUT STD_LOGIC;
                 signal CPU_data_master_qualified_request_clock_1_in : OUT STD_LOGIC;
                 signal CPU_data_master_read_data_valid_clock_1_in : OUT STD_LOGIC;
                 signal CPU_data_master_requests_clock_1_in : OUT STD_LOGIC;
                 signal clock_1_in_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clock_1_in_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_1_in_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal clock_1_in_read : OUT STD_LOGIC;
                 signal clock_1_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clock_1_in_reset_n : OUT STD_LOGIC;
                 signal clock_1_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_1_in_write : OUT STD_LOGIC;
                 signal clock_1_in_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_clock_1_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_1_in_arbitrator : entity is FALSE;
end entity clock_1_in_arbitrator;


architecture europa of clock_1_in_arbitrator is
                signal CPU_data_master_arbiterlock :  STD_LOGIC;
                signal CPU_data_master_arbiterlock2 :  STD_LOGIC;
                signal CPU_data_master_continuerequest :  STD_LOGIC;
                signal CPU_data_master_saved_grant_clock_1_in :  STD_LOGIC;
                signal clock_1_in_allgrants :  STD_LOGIC;
                signal clock_1_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_1_in_any_continuerequest :  STD_LOGIC;
                signal clock_1_in_arb_counter_enable :  STD_LOGIC;
                signal clock_1_in_arb_share_counter :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_arb_share_counter_next_value :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_arb_share_set_values :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_1_in_begins_xfer :  STD_LOGIC;
                signal clock_1_in_end_xfer :  STD_LOGIC;
                signal clock_1_in_firsttransfer :  STD_LOGIC;
                signal clock_1_in_grant_vector :  STD_LOGIC;
                signal clock_1_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_1_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_1_in_master_qreq_vector :  STD_LOGIC;
                signal clock_1_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_1_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_1_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_1_in_waits_for_read :  STD_LOGIC;
                signal clock_1_in_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_CPU_data_master_granted_clock_1_in :  STD_LOGIC;
                signal internal_CPU_data_master_qualified_request_clock_1_in :  STD_LOGIC;
                signal internal_CPU_data_master_requests_clock_1_in :  STD_LOGIC;
                signal internal_clock_1_in_waitrequest_from_sa :  STD_LOGIC;
                signal wait_for_clock_1_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_1_in_end_xfer;
      end if;
    end if;

  end process;

  clock_1_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_CPU_data_master_qualified_request_clock_1_in);
  --assign clock_1_in_readdata_from_sa = clock_1_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_1_in_readdata_from_sa <= clock_1_in_readdata;
  internal_CPU_data_master_requests_clock_1_in <= to_std_logic(((Std_Logic_Vector'(CPU_data_master_address_to_slave(23 DOWNTO 5) & std_logic_vector'("00000")) = std_logic_vector'("100000001000100001000000")))) AND ((CPU_data_master_read OR CPU_data_master_write));
  --assign clock_1_in_waitrequest_from_sa = clock_1_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_1_in_waitrequest_from_sa <= clock_1_in_waitrequest;
  --clock_1_in_arb_share_counter set values, which is an e_mux
  clock_1_in_arb_share_set_values <= std_logic_vector'("01");
  --clock_1_in_non_bursting_master_requests mux, which is an e_mux
  clock_1_in_non_bursting_master_requests <= internal_CPU_data_master_requests_clock_1_in;
  --clock_1_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_1_in_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(clock_1_in_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (clock_1_in_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(clock_1_in_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (clock_1_in_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
  --clock_1_in_allgrants all slave grants, which is an e_mux
  clock_1_in_allgrants <= clock_1_in_grant_vector;
  --clock_1_in_end_xfer assignment, which is an e_assign
  clock_1_in_end_xfer <= NOT ((clock_1_in_waits_for_read OR clock_1_in_waits_for_write));
  --clock_1_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_1_in_arb_counter_enable <= ((clock_1_in_end_xfer AND clock_1_in_allgrants)) OR ((clock_1_in_end_xfer AND NOT clock_1_in_non_bursting_master_requests));
  --clock_1_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_1_in_arb_share_counter <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(clock_1_in_arb_counter_enable) = '1' then 
        clock_1_in_arb_share_counter <= clock_1_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_1_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_1_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_1_in_master_qreq_vector AND clock_1_in_end_xfer)) OR ((clock_1_in_end_xfer AND NOT clock_1_in_non_bursting_master_requests)))) = '1' then 
        clock_1_in_slavearbiterlockenable <= or_reduce(clock_1_in_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --CPU/data_master clock_1/in arbiterlock, which is an e_assign
  CPU_data_master_arbiterlock <= clock_1_in_slavearbiterlockenable AND CPU_data_master_continuerequest;
  --clock_1_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_1_in_slavearbiterlockenable2 <= or_reduce(clock_1_in_arb_share_counter_next_value);
  --CPU/data_master clock_1/in arbiterlock2, which is an e_assign
  CPU_data_master_arbiterlock2 <= clock_1_in_slavearbiterlockenable2 AND CPU_data_master_continuerequest;
  --clock_1_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_1_in_any_continuerequest <= std_logic'('1');
  --CPU_data_master_continuerequest continued request, which is an e_assign
  CPU_data_master_continuerequest <= std_logic'('1');
  internal_CPU_data_master_qualified_request_clock_1_in <= internal_CPU_data_master_requests_clock_1_in AND NOT ((((CPU_data_master_read AND (NOT CPU_data_master_waitrequest))) OR (((NOT CPU_data_master_waitrequest) AND CPU_data_master_write))));
  --clock_1_in_writedata mux, which is an e_mux
  clock_1_in_writedata <= CPU_data_master_writedata (15 DOWNTO 0);
  --assign clock_1_in_endofpacket_from_sa = clock_1_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_1_in_endofpacket_from_sa <= clock_1_in_endofpacket;
  --master is always granted when requested
  internal_CPU_data_master_granted_clock_1_in <= internal_CPU_data_master_qualified_request_clock_1_in;
  --CPU/data_master saved-grant clock_1/in, which is an e_assign
  CPU_data_master_saved_grant_clock_1_in <= internal_CPU_data_master_requests_clock_1_in;
  --allow new arb cycle for clock_1/in, which is an e_assign
  clock_1_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_1_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_1_in_master_qreq_vector <= std_logic'('1');
  --clock_1_in_reset_n assignment, which is an e_assign
  clock_1_in_reset_n <= reset_n;
  --clock_1_in_firsttransfer first transaction, which is an e_assign
  clock_1_in_firsttransfer <= NOT ((clock_1_in_slavearbiterlockenable AND clock_1_in_any_continuerequest));
  --clock_1_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_1_in_beginbursttransfer_internal <= clock_1_in_begins_xfer AND clock_1_in_firsttransfer;
  --clock_1_in_read assignment, which is an e_mux
  clock_1_in_read <= internal_CPU_data_master_granted_clock_1_in AND CPU_data_master_read;
  --clock_1_in_write assignment, which is an e_mux
  clock_1_in_write <= internal_CPU_data_master_granted_clock_1_in AND CPU_data_master_write;
  --clock_1_in_address mux, which is an e_mux
  clock_1_in_address <= CPU_data_master_address_to_slave (3 DOWNTO 0);
  --slaveid clock_1_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_1_in_nativeaddress <= A_EXT (A_SRL(CPU_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 3);
  --d1_clock_1_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_1_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_1_in_end_xfer <= clock_1_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_1_in_waits_for_read in a cycle, which is an e_mux
  clock_1_in_waits_for_read <= clock_1_in_in_a_read_cycle AND internal_clock_1_in_waitrequest_from_sa;
  --clock_1_in_in_a_read_cycle assignment, which is an e_assign
  clock_1_in_in_a_read_cycle <= internal_CPU_data_master_granted_clock_1_in AND CPU_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_1_in_in_a_read_cycle;
  --clock_1_in_waits_for_write in a cycle, which is an e_mux
  clock_1_in_waits_for_write <= clock_1_in_in_a_write_cycle AND internal_clock_1_in_waitrequest_from_sa;
  --clock_1_in_in_a_write_cycle assignment, which is an e_assign
  clock_1_in_in_a_write_cycle <= internal_CPU_data_master_granted_clock_1_in AND CPU_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_1_in_in_a_write_cycle;
  wait_for_clock_1_in_counter <= std_logic'('0');
  --clock_1_in_byteenable byte enable port mux, which is an e_mux
  clock_1_in_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_CPU_data_master_granted_clock_1_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (CPU_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
  --vhdl renameroo for output signals
  CPU_data_master_granted_clock_1_in <= internal_CPU_data_master_granted_clock_1_in;
  --vhdl renameroo for output signals
  CPU_data_master_qualified_request_clock_1_in <= internal_CPU_data_master_qualified_request_clock_1_in;
  --vhdl renameroo for output signals
  CPU_data_master_requests_clock_1_in <= internal_CPU_data_master_requests_clock_1_in;
  --vhdl renameroo for output signals
  clock_1_in_waitrequest_from_sa <= internal_clock_1_in_waitrequest_from_sa;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_1_out_arbitrator is 
        port (
              -- inputs:
                 signal PLL_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clock_1_out_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clock_1_out_granted_PLL_s1 : IN STD_LOGIC;
                 signal clock_1_out_qualified_request_PLL_s1 : IN STD_LOGIC;
                 signal clock_1_out_read : IN STD_LOGIC;
                 signal clock_1_out_read_data_valid_PLL_s1 : IN STD_LOGIC;
                 signal clock_1_out_requests_PLL_s1 : IN STD_LOGIC;
                 signal clock_1_out_write : IN STD_LOGIC;
                 signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_PLL_s1_end_xfer : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_1_out_address_to_slave : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal clock_1_out_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal clock_1_out_reset_n : OUT STD_LOGIC;
                 signal clock_1_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_1_out_arbitrator : entity is FALSE;
end entity clock_1_out_arbitrator;


architecture europa of clock_1_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_1_out_address_last_time :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_1_out_read_last_time :  STD_LOGIC;
                signal clock_1_out_run :  STD_LOGIC;
                signal clock_1_out_write_last_time :  STD_LOGIC;
                signal clock_1_out_writedata_last_time :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_clock_1_out_address_to_slave :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal internal_clock_1_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_1_out_qualified_request_PLL_s1 OR NOT clock_1_out_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_PLL_s1_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_1_out_qualified_request_PLL_s1 OR NOT clock_1_out_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_out_write)))))))));
  --cascaded wait assignment, which is an e_assign
  clock_1_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_1_out_address_to_slave <= clock_1_out_address;
  --clock_1/out readdata mux, which is an e_mux
  clock_1_out_readdata <= PLL_s1_readdata_from_sa;
  --actual waitrequest port, which is an e_assign
  internal_clock_1_out_waitrequest <= NOT clock_1_out_run;
  --clock_1_out_reset_n assignment, which is an e_assign
  clock_1_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_1_out_address_to_slave <= internal_clock_1_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_1_out_waitrequest <= internal_clock_1_out_waitrequest;
--synthesis translate_off
    --clock_1_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_address_last_time <= std_logic_vector'("0000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_address_last_time <= clock_1_out_address;
        end if;
      end if;

    end process;

    --clock_1/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_1_out_waitrequest AND ((clock_1_out_read OR clock_1_out_write));
        end if;
      end if;

    end process;

    --clock_1_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_address, clock_1_out_address_last_time)
    VARIABLE write_line12 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_1_out_address /= clock_1_out_address_last_time))))) = '1' then 
          write(write_line12, now);
          write(write_line12, string'(": "));
          write(write_line12, string'("clock_1_out_address did not heed wait!!!"));
          write(output, write_line12.all);
          deallocate (write_line12);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_read_last_time <= clock_1_out_read;
        end if;
      end if;

    end process;

    --clock_1_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_read, clock_1_out_read_last_time)
    VARIABLE write_line13 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_1_out_read) /= std_logic'(clock_1_out_read_last_time)))))) = '1' then 
          write(write_line13, now);
          write(write_line13, string'(": "));
          write(write_line13, string'("clock_1_out_read did not heed wait!!!"));
          write(output, write_line13.all);
          deallocate (write_line13);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_write_last_time <= clock_1_out_write;
        end if;
      end if;

    end process;

    --clock_1_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_write, clock_1_out_write_last_time)
    VARIABLE write_line14 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_1_out_write) /= std_logic'(clock_1_out_write_last_time)))))) = '1' then 
          write(write_line14, now);
          write(write_line14, string'(": "));
          write(write_line14, string'("clock_1_out_write did not heed wait!!!"));
          write(output, write_line14.all);
          deallocate (write_line14);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_writedata_last_time <= std_logic_vector'("0000000000000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_writedata_last_time <= clock_1_out_writedata;
        end if;
      end if;

    end process;

    --clock_1_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_write, clock_1_out_writedata, clock_1_out_writedata_last_time)
    VARIABLE write_line15 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_1_out_writedata /= clock_1_out_writedata_last_time)))) AND clock_1_out_write)) = '1' then 
          write(write_line15, now);
          write(write_line15, string'(": "));
          write(write_line15, string'("clock_1_out_writedata did not heed wait!!!"));
          write(output, write_line15.all);
          deallocate (write_line15);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity NIOS_II_reset_clk_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity NIOS_II_reset_clk_domain_synch_module;


architecture europa of NIOS_II_reset_clk_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity NIOS_II is 
        port (
              -- 1) global signals:
                 signal clk : IN STD_LOGIC;
                 signal clk_25 : OUT STD_LOGIC;
                 signal clk_25_180 : OUT STD_LOGIC;
                 signal clk_90 : OUT STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- the_AVALON
                 signal acknowledge_to_the_AVALON : IN STD_LOGIC;
                 signal address_from_the_AVALON : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal bus_enable_from_the_AVALON : OUT STD_LOGIC;
                 signal byte_enable_from_the_AVALON : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal irq_to_the_AVALON : IN STD_LOGIC;
                 signal read_data_to_the_AVALON : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal rw_from_the_AVALON : OUT STD_LOGIC;
                 signal write_data_from_the_AVALON : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

              -- the_IRDA
                 signal rxd_to_the_IRDA : IN STD_LOGIC;
                 signal txd_from_the_IRDA : OUT STD_LOGIC;

              -- the_KEYS
                 signal in_port_to_the_KEYS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

              -- the_LCD
                 signal LCD_E_from_the_LCD : OUT STD_LOGIC;
                 signal LCD_RS_from_the_LCD : OUT STD_LOGIC;
                 signal LCD_RW_from_the_LCD : OUT STD_LOGIC;
                 signal LCD_data_to_and_from_the_LCD : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

              -- the_SDRAM
                 signal zs_addr_from_the_SDRAM : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal zs_ba_from_the_SDRAM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal zs_cas_n_from_the_SDRAM : OUT STD_LOGIC;
                 signal zs_cke_from_the_SDRAM : OUT STD_LOGIC;
                 signal zs_cs_n_from_the_SDRAM : OUT STD_LOGIC;
                 signal zs_dq_to_and_from_the_SDRAM : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal zs_dqm_from_the_SDRAM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal zs_ras_n_from_the_SDRAM : OUT STD_LOGIC;
                 signal zs_we_n_from_the_SDRAM : OUT STD_LOGIC;

              -- the_SWITCHES
                 signal in_port_to_the_SWITCHES : IN STD_LOGIC_VECTOR (17 DOWNTO 0);

              -- the_VGA
                 signal VGA_BLANK_from_the_VGA : OUT STD_LOGIC;
                 signal VGA_B_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal VGA_G_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal VGA_HS_from_the_VGA : OUT STD_LOGIC;
                 signal VGA_R_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal VGA_SYNC_from_the_VGA : OUT STD_LOGIC;
                 signal VGA_VS_from_the_VGA : OUT STD_LOGIC
              );
end entity NIOS_II;


architecture europa of NIOS_II is
component AVALON_avalon_slave_arbitrator is 
           port (
                 -- inputs:
                    signal AVALON_avalon_slave_irq : IN STD_LOGIC;
                    signal AVALON_avalon_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal AVALON_avalon_slave_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                    signal CPU_instruction_master_read : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal AVALON_avalon_slave_address : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal AVALON_avalon_slave_chipselect : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_irq_from_sa : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_read : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal AVALON_avalon_slave_waitrequest_from_sa : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_write : OUT STD_LOGIC;
                    signal AVALON_avalon_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_data_master_granted_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_data_master_requests_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_instruction_master_granted_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal CPU_instruction_master_requests_AVALON_avalon_slave : OUT STD_LOGIC;
                    signal d1_AVALON_avalon_slave_end_xfer : OUT STD_LOGIC;
                    signal registered_CPU_data_master_read_data_valid_AVALON_avalon_slave : OUT STD_LOGIC
                 );
end component AVALON_avalon_slave_arbitrator;

component NIOS_II_reset_clk_90_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component NIOS_II_reset_clk_90_domain_synch_module;

component AVALON is 
           port (
                 -- inputs:
                    signal acknowledge : IN STD_LOGIC;
                    signal avalon_address : IN STD_LOGIC;
                    signal avalon_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal avalon_chipselect : IN STD_LOGIC;
                    signal avalon_read : IN STD_LOGIC;
                    signal avalon_write : IN STD_LOGIC;
                    signal avalon_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal irq : IN STD_LOGIC;
                    signal read_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset : IN STD_LOGIC;

                 -- outputs:
                    signal address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal avalon_irq : OUT STD_LOGIC;
                    signal avalon_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal avalon_waitrequest : OUT STD_LOGIC;
                    signal bus_enable : OUT STD_LOGIC;
                    signal byte_enable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal rw : OUT STD_LOGIC;
                    signal write_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component AVALON;

component CPU_jtag_debug_module_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_debugaccess : IN STD_LOGIC;
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                    signal CPU_instruction_master_read : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                    signal CPU_jtag_debug_module_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_jtag_debug_module_resetrequest : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_data_master_requests_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_instruction_master_granted_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_instruction_master_requests_CPU_jtag_debug_module : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                    signal CPU_jtag_debug_module_begintransfer : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_jtag_debug_module_chipselect : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_debugaccess : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_jtag_debug_module_reset : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_reset_n : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_resetrequest_from_sa : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_write : OUT STD_LOGIC;
                    signal CPU_jtag_debug_module_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_CPU_jtag_debug_module_end_xfer : OUT STD_LOGIC
                 );
end component CPU_jtag_debug_module_arbitrator;

component CPU_data_master_arbitrator is 
           port (
                 -- inputs:
                    signal AVALON_avalon_slave_irq_from_sa : IN STD_LOGIC;
                    signal AVALON_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal AVALON_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
                    signal CPU_data_master_address : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable_SDRAM_s1 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_data_master_debugaccess : IN STD_LOGIC;
                    signal CPU_data_master_granted_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_data_master_granted_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_data_master_granted_IRDA_s1 : IN STD_LOGIC;
                    signal CPU_data_master_granted_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                    signal CPU_data_master_granted_KEYS_s1 : IN STD_LOGIC;
                    signal CPU_data_master_granted_LCD_control_slave : IN STD_LOGIC;
                    signal CPU_data_master_granted_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_data_master_granted_SWITCHES_s1 : IN STD_LOGIC;
                    signal CPU_data_master_granted_TIMER0_s1 : IN STD_LOGIC;
                    signal CPU_data_master_granted_clock_0_in : IN STD_LOGIC;
                    signal CPU_data_master_granted_clock_1_in : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_IRDA_s1 : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_KEYS_s1 : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_LCD_control_slave : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_SWITCHES_s1 : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_TIMER0_s1 : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_clock_0_in : IN STD_LOGIC;
                    signal CPU_data_master_qualified_request_clock_1_in : IN STD_LOGIC;
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_IRDA_s1 : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_KEYS_s1 : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_LCD_control_slave : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SWITCHES_s1 : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_TIMER0_s1 : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_clock_0_in : IN STD_LOGIC;
                    signal CPU_data_master_read_data_valid_clock_1_in : IN STD_LOGIC;
                    signal CPU_data_master_requests_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_data_master_requests_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_data_master_requests_IRDA_s1 : IN STD_LOGIC;
                    signal CPU_data_master_requests_JTAG_avalon_jtag_slave : IN STD_LOGIC;
                    signal CPU_data_master_requests_KEYS_s1 : IN STD_LOGIC;
                    signal CPU_data_master_requests_LCD_control_slave : IN STD_LOGIC;
                    signal CPU_data_master_requests_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_data_master_requests_SWITCHES_s1 : IN STD_LOGIC;
                    signal CPU_data_master_requests_TIMER0_s1 : IN STD_LOGIC;
                    signal CPU_data_master_requests_clock_0_in : IN STD_LOGIC;
                    signal CPU_data_master_requests_clock_1_in : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal IRDA_s1_irq_from_sa : IN STD_LOGIC;
                    signal IRDA_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal JTAG_avalon_jtag_slave_irq_from_sa : IN STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal JTAG_avalon_jtag_slave_waitrequest_from_sa : IN STD_LOGIC;
                    signal KEYS_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal LCD_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal LCD_control_slave_wait_counter_eq_0 : IN STD_LOGIC;
                    signal LCD_control_slave_wait_counter_eq_1 : IN STD_LOGIC;
                    signal SDRAM_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal SDRAM_s1_waitrequest_from_sa : IN STD_LOGIC;
                    signal SWITCHES_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal TIMER0_s1_irq_from_sa : IN STD_LOGIC;
                    signal TIMER0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_0_in_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clock_0_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal clock_1_in_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clock_1_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal d1_AVALON_avalon_slave_end_xfer : IN STD_LOGIC;
                    signal d1_CPU_jtag_debug_module_end_xfer : IN STD_LOGIC;
                    signal d1_IRDA_s1_end_xfer : IN STD_LOGIC;
                    signal d1_JTAG_avalon_jtag_slave_end_xfer : IN STD_LOGIC;
                    signal d1_KEYS_s1_end_xfer : IN STD_LOGIC;
                    signal d1_LCD_control_slave_end_xfer : IN STD_LOGIC;
                    signal d1_SDRAM_s1_end_xfer : IN STD_LOGIC;
                    signal d1_SWITCHES_s1_end_xfer : IN STD_LOGIC;
                    signal d1_TIMER0_s1_end_xfer : IN STD_LOGIC;
                    signal d1_clock_0_in_end_xfer : IN STD_LOGIC;
                    signal d1_clock_1_in_end_xfer : IN STD_LOGIC;
                    signal registered_CPU_data_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_address_to_slave : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_data_master_dbs_write_16 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal CPU_data_master_irq : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_data_master_no_byte_enables_and_last_term : OUT STD_LOGIC;
                    signal CPU_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_data_master_waitrequest : OUT STD_LOGIC
                 );
end component CPU_data_master_arbitrator;

component CPU_instruction_master_arbitrator is 
           port (
                 -- inputs:
                    signal AVALON_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal AVALON_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
                    signal CPU_instruction_master_address : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_instruction_master_granted_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_instruction_master_granted_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_instruction_master_granted_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_instruction_master_read : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : IN STD_LOGIC;
                    signal CPU_instruction_master_requests_AVALON_avalon_slave : IN STD_LOGIC;
                    signal CPU_instruction_master_requests_CPU_jtag_debug_module : IN STD_LOGIC;
                    signal CPU_instruction_master_requests_SDRAM_s1 : IN STD_LOGIC;
                    signal CPU_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal SDRAM_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal SDRAM_s1_waitrequest_from_sa : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal d1_AVALON_avalon_slave_end_xfer : IN STD_LOGIC;
                    signal d1_CPU_jtag_debug_module_end_xfer : IN STD_LOGIC;
                    signal d1_SDRAM_s1_end_xfer : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_instruction_master_address_to_slave : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_instruction_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_instruction_master_latency_counter : OUT STD_LOGIC;
                    signal CPU_instruction_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal CPU_instruction_master_readdatavalid : OUT STD_LOGIC;
                    signal CPU_instruction_master_waitrequest : OUT STD_LOGIC
                 );
end component CPU_instruction_master_arbitrator;

component CPU is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal d_irq : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d_waitrequest : IN STD_LOGIC;
                    signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal i_readdatavalid : IN STD_LOGIC;
                    signal i_waitrequest : IN STD_LOGIC;
                    signal jtag_debug_module_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
                    signal jtag_debug_module_begintransfer : IN STD_LOGIC;
                    signal jtag_debug_module_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal jtag_debug_module_clk : IN STD_LOGIC;
                    signal jtag_debug_module_debugaccess : IN STD_LOGIC;
                    signal jtag_debug_module_reset : IN STD_LOGIC;
                    signal jtag_debug_module_select : IN STD_LOGIC;
                    signal jtag_debug_module_write : IN STD_LOGIC;
                    signal jtag_debug_module_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal d_address : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal d_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal d_read : OUT STD_LOGIC;
                    signal d_write : OUT STD_LOGIC;
                    signal d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal i_address : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal i_read : OUT STD_LOGIC;
                    signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
                    signal jtag_debug_module_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_debug_module_resetrequest : OUT STD_LOGIC
                 );
end component CPU;

component IRDA_s1_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal IRDA_s1_dataavailable : IN STD_LOGIC;
                    signal IRDA_s1_irq : IN STD_LOGIC;
                    signal IRDA_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal IRDA_s1_readyfordata : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_IRDA_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_IRDA_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_IRDA_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_requests_IRDA_s1 : OUT STD_LOGIC;
                    signal IRDA_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal IRDA_s1_begintransfer : OUT STD_LOGIC;
                    signal IRDA_s1_chipselect : OUT STD_LOGIC;
                    signal IRDA_s1_dataavailable_from_sa : OUT STD_LOGIC;
                    signal IRDA_s1_irq_from_sa : OUT STD_LOGIC;
                    signal IRDA_s1_read_n : OUT STD_LOGIC;
                    signal IRDA_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal IRDA_s1_readyfordata_from_sa : OUT STD_LOGIC;
                    signal IRDA_s1_reset_n : OUT STD_LOGIC;
                    signal IRDA_s1_write_n : OUT STD_LOGIC;
                    signal IRDA_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_IRDA_s1_end_xfer : OUT STD_LOGIC
                 );
end component IRDA_s1_arbitrator;

component IRDA is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read_n : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal rxd : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal dataavailable : OUT STD_LOGIC;
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal readyfordata : OUT STD_LOGIC;
                    signal txd : OUT STD_LOGIC
                 );
end component IRDA;

component JTAG_avalon_jtag_slave_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal JTAG_avalon_jtag_slave_dataavailable : IN STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_irq : IN STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal JTAG_avalon_jtag_slave_readyfordata : IN STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_waitrequest : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                    signal CPU_data_master_requests_JTAG_avalon_jtag_slave : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_address : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_chipselect : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_dataavailable_from_sa : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_irq_from_sa : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_read_n : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal JTAG_avalon_jtag_slave_readyfordata_from_sa : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_reset_n : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_waitrequest_from_sa : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_write_n : OUT STD_LOGIC;
                    signal JTAG_avalon_jtag_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_JTAG_avalon_jtag_slave_end_xfer : OUT STD_LOGIC
                 );
end component JTAG_avalon_jtag_slave_arbitrator;

component JTAG is 
           port (
                 -- inputs:
                    signal av_address : IN STD_LOGIC;
                    signal av_chipselect : IN STD_LOGIC;
                    signal av_read_n : IN STD_LOGIC;
                    signal av_write_n : IN STD_LOGIC;
                    signal av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal rst_n : IN STD_LOGIC;

                 -- outputs:
                    signal av_irq : OUT STD_LOGIC;
                    signal av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal av_waitrequest : OUT STD_LOGIC;
                    signal dataavailable : OUT STD_LOGIC;
                    signal readyfordata : OUT STD_LOGIC
                 );
end component JTAG;

component KEYS_s1_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal KEYS_s1_readdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_KEYS_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_KEYS_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_KEYS_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_requests_KEYS_s1 : OUT STD_LOGIC;
                    signal KEYS_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal KEYS_s1_chipselect : OUT STD_LOGIC;
                    signal KEYS_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal KEYS_s1_reset_n : OUT STD_LOGIC;
                    signal KEYS_s1_write_n : OUT STD_LOGIC;
                    signal KEYS_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal d1_KEYS_s1_end_xfer : OUT STD_LOGIC
                 );
end component KEYS_s1_arbitrator;

component KEYS is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal in_port : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- outputs:
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component KEYS;

component LCD_control_slave_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal LCD_control_slave_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_LCD_control_slave : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_LCD_control_slave : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_LCD_control_slave : OUT STD_LOGIC;
                    signal CPU_data_master_requests_LCD_control_slave : OUT STD_LOGIC;
                    signal LCD_control_slave_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal LCD_control_slave_begintransfer : OUT STD_LOGIC;
                    signal LCD_control_slave_read : OUT STD_LOGIC;
                    signal LCD_control_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal LCD_control_slave_wait_counter_eq_0 : OUT STD_LOGIC;
                    signal LCD_control_slave_wait_counter_eq_1 : OUT STD_LOGIC;
                    signal LCD_control_slave_write : OUT STD_LOGIC;
                    signal LCD_control_slave_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal d1_LCD_control_slave_end_xfer : OUT STD_LOGIC
                 );
end component LCD_control_slave_arbitrator;

component LCD is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal LCD_E : OUT STD_LOGIC;
                    signal LCD_RS : OUT STD_LOGIC;
                    signal LCD_RW : OUT STD_LOGIC;
                    signal LCD_data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component LCD;

component PLL_s1_arbitrator is 
           port (
                 -- inputs:
                    signal PLL_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal PLL_s1_resetrequest : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clock_1_out_address_to_slave : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clock_1_out_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal clock_1_out_read : IN STD_LOGIC;
                    signal clock_1_out_write : IN STD_LOGIC;
                    signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal PLL_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal PLL_s1_chipselect : OUT STD_LOGIC;
                    signal PLL_s1_read : OUT STD_LOGIC;
                    signal PLL_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal PLL_s1_reset_n : OUT STD_LOGIC;
                    signal PLL_s1_resetrequest_from_sa : OUT STD_LOGIC;
                    signal PLL_s1_write : OUT STD_LOGIC;
                    signal PLL_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clock_1_out_granted_PLL_s1 : OUT STD_LOGIC;
                    signal clock_1_out_qualified_request_PLL_s1 : OUT STD_LOGIC;
                    signal clock_1_out_read_data_valid_PLL_s1 : OUT STD_LOGIC;
                    signal clock_1_out_requests_PLL_s1 : OUT STD_LOGIC;
                    signal d1_PLL_s1_end_xfer : OUT STD_LOGIC
                 );
end component PLL_s1_arbitrator;

component PLL is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal c0 : OUT STD_LOGIC;
                    signal c1 : OUT STD_LOGIC;
                    signal c2 : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal resetrequest : OUT STD_LOGIC
                 );
end component PLL;

component SDRAM_s1_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_data_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal CPU_data_master_no_byte_enables_and_last_term : IN STD_LOGIC;
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_instruction_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_instruction_master_latency_counter : IN STD_LOGIC;
                    signal CPU_instruction_master_read : IN STD_LOGIC;
                    signal SDRAM_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal SDRAM_s1_readdatavalid : IN STD_LOGIC;
                    signal SDRAM_s1_waitrequest : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_byteenable_SDRAM_s1 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal CPU_data_master_granted_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SDRAM_s1_shift_register : OUT STD_LOGIC;
                    signal CPU_data_master_requests_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_instruction_master_granted_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_instruction_master_qualified_request_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1 : OUT STD_LOGIC;
                    signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register : OUT STD_LOGIC;
                    signal CPU_instruction_master_requests_SDRAM_s1 : OUT STD_LOGIC;
                    signal SDRAM_s1_address : OUT STD_LOGIC_VECTOR (21 DOWNTO 0);
                    signal SDRAM_s1_byteenable_n : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal SDRAM_s1_chipselect : OUT STD_LOGIC;
                    signal SDRAM_s1_read_n : OUT STD_LOGIC;
                    signal SDRAM_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal SDRAM_s1_reset_n : OUT STD_LOGIC;
                    signal SDRAM_s1_waitrequest_from_sa : OUT STD_LOGIC;
                    signal SDRAM_s1_write_n : OUT STD_LOGIC;
                    signal SDRAM_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_SDRAM_s1_end_xfer : OUT STD_LOGIC
                 );
end component SDRAM_s1_arbitrator;

component SDRAM is 
           port (
                 -- inputs:
                    signal az_addr : IN STD_LOGIC_VECTOR (21 DOWNTO 0);
                    signal az_be_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal az_cs : IN STD_LOGIC;
                    signal az_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal az_rd_n : IN STD_LOGIC;
                    signal az_wr_n : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal za_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal za_valid : OUT STD_LOGIC;
                    signal za_waitrequest : OUT STD_LOGIC;
                    signal zs_addr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
                    signal zs_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_cas_n : OUT STD_LOGIC;
                    signal zs_cke : OUT STD_LOGIC;
                    signal zs_cs_n : OUT STD_LOGIC;
                    signal zs_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal zs_dqm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_ras_n : OUT STD_LOGIC;
                    signal zs_we_n : OUT STD_LOGIC
                 );
end component SDRAM;

component SWITCHES_s1_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal SWITCHES_s1_readdata : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_SWITCHES_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_SWITCHES_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_SWITCHES_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_requests_SWITCHES_s1 : OUT STD_LOGIC;
                    signal SWITCHES_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal SWITCHES_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal SWITCHES_s1_reset_n : OUT STD_LOGIC;
                    signal d1_SWITCHES_s1_end_xfer : OUT STD_LOGIC
                 );
end component SWITCHES_s1_arbitrator;

component SWITCHES is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal in_port : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal readdata : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
                 );
end component SWITCHES;

component TIMER0_s1_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal TIMER0_s1_irq : IN STD_LOGIC;
                    signal TIMER0_s1_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_TIMER0_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_TIMER0_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_TIMER0_s1 : OUT STD_LOGIC;
                    signal CPU_data_master_requests_TIMER0_s1 : OUT STD_LOGIC;
                    signal TIMER0_s1_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal TIMER0_s1_chipselect : OUT STD_LOGIC;
                    signal TIMER0_s1_irq_from_sa : OUT STD_LOGIC;
                    signal TIMER0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal TIMER0_s1_reset_n : OUT STD_LOGIC;
                    signal TIMER0_s1_write_n : OUT STD_LOGIC;
                    signal TIMER0_s1_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_TIMER0_s1_end_xfer : OUT STD_LOGIC
                 );
end component TIMER0_s1_arbitrator;

component TIMER0 is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component TIMER0;

component VGA_avalon_character_slave_arbitrator is 
           port (
                 -- inputs:
                    signal VGA_avalon_character_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_0_out_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal clock_0_out_read : IN STD_LOGIC;
                    signal clock_0_out_write : IN STD_LOGIC;
                    signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal VGA_avalon_character_slave_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal VGA_avalon_character_slave_chipselect : OUT STD_LOGIC;
                    signal VGA_avalon_character_slave_read : OUT STD_LOGIC;
                    signal VGA_avalon_character_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal VGA_avalon_character_slave_write : OUT STD_LOGIC;
                    signal VGA_avalon_character_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clock_0_out_granted_VGA_avalon_character_slave : OUT STD_LOGIC;
                    signal clock_0_out_qualified_request_VGA_avalon_character_slave : OUT STD_LOGIC;
                    signal clock_0_out_read_data_valid_VGA_avalon_character_slave : OUT STD_LOGIC;
                    signal clock_0_out_requests_VGA_avalon_character_slave : OUT STD_LOGIC;
                    signal d1_VGA_avalon_character_slave_end_xfer : OUT STD_LOGIC
                 );
end component VGA_avalon_character_slave_arbitrator;

component NIOS_II_reset_clk_25_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component NIOS_II_reset_clk_25_domain_synch_module;

component VGA is 
           port (
                 -- inputs:
                    signal char_address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal char_chipselect : IN STD_LOGIC;
                    signal char_clk : IN STD_LOGIC;
                    signal char_read : IN STD_LOGIC;
                    signal char_write : IN STD_LOGIC;
                    signal char_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset : IN STD_LOGIC;
                    signal vga_dac_clk : IN STD_LOGIC;

                 -- outputs:
                    signal VGA_B : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_BLANK : OUT STD_LOGIC;
                    signal VGA_G : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_HS : OUT STD_LOGIC;
                    signal VGA_R : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_SYNC : OUT STD_LOGIC;
                    signal VGA_VS : OUT STD_LOGIC;
                    signal char_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component VGA;

component clock_0_in_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_0_in_endofpacket : IN STD_LOGIC;
                    signal clock_0_in_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clock_0_in_waitrequest : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_clock_0_in : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_clock_0_in : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_clock_0_in : OUT STD_LOGIC;
                    signal CPU_data_master_requests_clock_0_in : OUT STD_LOGIC;
                    signal clock_0_in_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal clock_0_in_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clock_0_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_0_in_nativeaddress : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal clock_0_in_read : OUT STD_LOGIC;
                    signal clock_0_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clock_0_in_reset_n : OUT STD_LOGIC;
                    signal clock_0_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_0_in_write : OUT STD_LOGIC;
                    signal clock_0_in_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_clock_0_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_0_in_arbitrator;

component clock_0_out_arbitrator is 
           port (
                 -- inputs:
                    signal VGA_avalon_character_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_0_out_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal clock_0_out_granted_VGA_avalon_character_slave : IN STD_LOGIC;
                    signal clock_0_out_qualified_request_VGA_avalon_character_slave : IN STD_LOGIC;
                    signal clock_0_out_read : IN STD_LOGIC;
                    signal clock_0_out_read_data_valid_VGA_avalon_character_slave : IN STD_LOGIC;
                    signal clock_0_out_requests_VGA_avalon_character_slave : IN STD_LOGIC;
                    signal clock_0_out_write : IN STD_LOGIC;
                    signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_VGA_avalon_character_slave_end_xfer : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_0_out_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal clock_0_out_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clock_0_out_reset_n : OUT STD_LOGIC;
                    signal clock_0_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_0_out_arbitrator;

component clock_0 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal slave_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
                    signal master_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_0;

component clock_1_in_arbitrator is 
           port (
                 -- inputs:
                    signal CPU_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                    signal CPU_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal CPU_data_master_read : IN STD_LOGIC;
                    signal CPU_data_master_waitrequest : IN STD_LOGIC;
                    signal CPU_data_master_write : IN STD_LOGIC;
                    signal CPU_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_1_in_endofpacket : IN STD_LOGIC;
                    signal clock_1_in_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clock_1_in_waitrequest : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal CPU_data_master_granted_clock_1_in : OUT STD_LOGIC;
                    signal CPU_data_master_qualified_request_clock_1_in : OUT STD_LOGIC;
                    signal CPU_data_master_read_data_valid_clock_1_in : OUT STD_LOGIC;
                    signal CPU_data_master_requests_clock_1_in : OUT STD_LOGIC;
                    signal clock_1_in_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clock_1_in_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_1_in_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal clock_1_in_read : OUT STD_LOGIC;
                    signal clock_1_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clock_1_in_reset_n : OUT STD_LOGIC;
                    signal clock_1_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_1_in_write : OUT STD_LOGIC;
                    signal clock_1_in_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_clock_1_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_1_in_arbitrator;

component clock_1_out_arbitrator is 
           port (
                 -- inputs:
                    signal PLL_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal clock_1_out_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clock_1_out_granted_PLL_s1 : IN STD_LOGIC;
                    signal clock_1_out_qualified_request_PLL_s1 : IN STD_LOGIC;
                    signal clock_1_out_read : IN STD_LOGIC;
                    signal clock_1_out_read_data_valid_PLL_s1 : IN STD_LOGIC;
                    signal clock_1_out_requests_PLL_s1 : IN STD_LOGIC;
                    signal clock_1_out_write : IN STD_LOGIC;
                    signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_PLL_s1_end_xfer : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_1_out_address_to_slave : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal clock_1_out_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal clock_1_out_reset_n : OUT STD_LOGIC;
                    signal clock_1_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_1_out_arbitrator;

component clock_1 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal slave_byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal master_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_1;

component NIOS_II_reset_clk_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component NIOS_II_reset_clk_domain_synch_module;

                signal AVALON_avalon_slave_address :  STD_LOGIC;
                signal AVALON_avalon_slave_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal AVALON_avalon_slave_chipselect :  STD_LOGIC;
                signal AVALON_avalon_slave_irq :  STD_LOGIC;
                signal AVALON_avalon_slave_irq_from_sa :  STD_LOGIC;
                signal AVALON_avalon_slave_read :  STD_LOGIC;
                signal AVALON_avalon_slave_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal AVALON_avalon_slave_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal AVALON_avalon_slave_waitrequest :  STD_LOGIC;
                signal AVALON_avalon_slave_waitrequest_from_sa :  STD_LOGIC;
                signal AVALON_avalon_slave_write :  STD_LOGIC;
                signal AVALON_avalon_slave_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_data_master_address :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal CPU_data_master_address_to_slave :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal CPU_data_master_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal CPU_data_master_byteenable_SDRAM_s1 :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_data_master_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_data_master_dbs_write_16 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal CPU_data_master_debugaccess :  STD_LOGIC;
                signal CPU_data_master_granted_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_data_master_granted_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_data_master_granted_IRDA_s1 :  STD_LOGIC;
                signal CPU_data_master_granted_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal CPU_data_master_granted_KEYS_s1 :  STD_LOGIC;
                signal CPU_data_master_granted_LCD_control_slave :  STD_LOGIC;
                signal CPU_data_master_granted_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_granted_SWITCHES_s1 :  STD_LOGIC;
                signal CPU_data_master_granted_TIMER0_s1 :  STD_LOGIC;
                signal CPU_data_master_granted_clock_0_in :  STD_LOGIC;
                signal CPU_data_master_granted_clock_1_in :  STD_LOGIC;
                signal CPU_data_master_irq :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_data_master_no_byte_enables_and_last_term :  STD_LOGIC;
                signal CPU_data_master_qualified_request_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_data_master_qualified_request_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_data_master_qualified_request_IRDA_s1 :  STD_LOGIC;
                signal CPU_data_master_qualified_request_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal CPU_data_master_qualified_request_KEYS_s1 :  STD_LOGIC;
                signal CPU_data_master_qualified_request_LCD_control_slave :  STD_LOGIC;
                signal CPU_data_master_qualified_request_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_qualified_request_SWITCHES_s1 :  STD_LOGIC;
                signal CPU_data_master_qualified_request_TIMER0_s1 :  STD_LOGIC;
                signal CPU_data_master_qualified_request_clock_0_in :  STD_LOGIC;
                signal CPU_data_master_qualified_request_clock_1_in :  STD_LOGIC;
                signal CPU_data_master_read :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_IRDA_s1 :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_KEYS_s1 :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_LCD_control_slave :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_SDRAM_s1_shift_register :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_SWITCHES_s1 :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_TIMER0_s1 :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_clock_0_in :  STD_LOGIC;
                signal CPU_data_master_read_data_valid_clock_1_in :  STD_LOGIC;
                signal CPU_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_data_master_requests_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_data_master_requests_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_data_master_requests_IRDA_s1 :  STD_LOGIC;
                signal CPU_data_master_requests_JTAG_avalon_jtag_slave :  STD_LOGIC;
                signal CPU_data_master_requests_KEYS_s1 :  STD_LOGIC;
                signal CPU_data_master_requests_LCD_control_slave :  STD_LOGIC;
                signal CPU_data_master_requests_SDRAM_s1 :  STD_LOGIC;
                signal CPU_data_master_requests_SWITCHES_s1 :  STD_LOGIC;
                signal CPU_data_master_requests_TIMER0_s1 :  STD_LOGIC;
                signal CPU_data_master_requests_clock_0_in :  STD_LOGIC;
                signal CPU_data_master_requests_clock_1_in :  STD_LOGIC;
                signal CPU_data_master_waitrequest :  STD_LOGIC;
                signal CPU_data_master_write :  STD_LOGIC;
                signal CPU_data_master_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_instruction_master_address :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal CPU_instruction_master_address_to_slave :  STD_LOGIC_VECTOR (23 DOWNTO 0);
                signal CPU_instruction_master_dbs_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal CPU_instruction_master_granted_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_instruction_master_granted_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_instruction_master_granted_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_latency_counter :  STD_LOGIC;
                signal CPU_instruction_master_qualified_request_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_instruction_master_qualified_request_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_instruction_master_qualified_request_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_read :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register :  STD_LOGIC;
                signal CPU_instruction_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_instruction_master_readdatavalid :  STD_LOGIC;
                signal CPU_instruction_master_requests_AVALON_avalon_slave :  STD_LOGIC;
                signal CPU_instruction_master_requests_CPU_jtag_debug_module :  STD_LOGIC;
                signal CPU_instruction_master_requests_SDRAM_s1 :  STD_LOGIC;
                signal CPU_instruction_master_waitrequest :  STD_LOGIC;
                signal CPU_jtag_debug_module_address :  STD_LOGIC_VECTOR (8 DOWNTO 0);
                signal CPU_jtag_debug_module_begintransfer :  STD_LOGIC;
                signal CPU_jtag_debug_module_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal CPU_jtag_debug_module_chipselect :  STD_LOGIC;
                signal CPU_jtag_debug_module_debugaccess :  STD_LOGIC;
                signal CPU_jtag_debug_module_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_jtag_debug_module_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal CPU_jtag_debug_module_reset :  STD_LOGIC;
                signal CPU_jtag_debug_module_reset_n :  STD_LOGIC;
                signal CPU_jtag_debug_module_resetrequest :  STD_LOGIC;
                signal CPU_jtag_debug_module_resetrequest_from_sa :  STD_LOGIC;
                signal CPU_jtag_debug_module_write :  STD_LOGIC;
                signal CPU_jtag_debug_module_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal IRDA_s1_address :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal IRDA_s1_begintransfer :  STD_LOGIC;
                signal IRDA_s1_chipselect :  STD_LOGIC;
                signal IRDA_s1_dataavailable :  STD_LOGIC;
                signal IRDA_s1_dataavailable_from_sa :  STD_LOGIC;
                signal IRDA_s1_irq :  STD_LOGIC;
                signal IRDA_s1_irq_from_sa :  STD_LOGIC;
                signal IRDA_s1_read_n :  STD_LOGIC;
                signal IRDA_s1_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal IRDA_s1_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal IRDA_s1_readyfordata :  STD_LOGIC;
                signal IRDA_s1_readyfordata_from_sa :  STD_LOGIC;
                signal IRDA_s1_reset_n :  STD_LOGIC;
                signal IRDA_s1_write_n :  STD_LOGIC;
                signal IRDA_s1_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_address :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_chipselect :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_dataavailable :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_dataavailable_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_irq :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_irq_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_read_n :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal JTAG_avalon_jtag_slave_readyfordata :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_readyfordata_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_reset_n :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_waitrequest :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_waitrequest_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_write_n :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal KEYS_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal KEYS_s1_chipselect :  STD_LOGIC;
                signal KEYS_s1_irq :  STD_LOGIC;
                signal KEYS_s1_readdata :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal KEYS_s1_readdata_from_sa :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal KEYS_s1_reset_n :  STD_LOGIC;
                signal KEYS_s1_write_n :  STD_LOGIC;
                signal KEYS_s1_writedata :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal LCD_control_slave_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal LCD_control_slave_begintransfer :  STD_LOGIC;
                signal LCD_control_slave_irq :  STD_LOGIC;
                signal LCD_control_slave_read :  STD_LOGIC;
                signal LCD_control_slave_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal LCD_control_slave_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal LCD_control_slave_wait_counter_eq_0 :  STD_LOGIC;
                signal LCD_control_slave_wait_counter_eq_1 :  STD_LOGIC;
                signal LCD_control_slave_write :  STD_LOGIC;
                signal LCD_control_slave_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal PLL_s1_address :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal PLL_s1_chipselect :  STD_LOGIC;
                signal PLL_s1_read :  STD_LOGIC;
                signal PLL_s1_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal PLL_s1_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal PLL_s1_reset_n :  STD_LOGIC;
                signal PLL_s1_resetrequest :  STD_LOGIC;
                signal PLL_s1_resetrequest_from_sa :  STD_LOGIC;
                signal PLL_s1_write :  STD_LOGIC;
                signal PLL_s1_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal SDRAM_s1_address :  STD_LOGIC_VECTOR (21 DOWNTO 0);
                signal SDRAM_s1_byteenable_n :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SDRAM_s1_chipselect :  STD_LOGIC;
                signal SDRAM_s1_read_n :  STD_LOGIC;
                signal SDRAM_s1_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal SDRAM_s1_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal SDRAM_s1_readdatavalid :  STD_LOGIC;
                signal SDRAM_s1_reset_n :  STD_LOGIC;
                signal SDRAM_s1_waitrequest :  STD_LOGIC;
                signal SDRAM_s1_waitrequest_from_sa :  STD_LOGIC;
                signal SDRAM_s1_write_n :  STD_LOGIC;
                signal SDRAM_s1_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal SWITCHES_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal SWITCHES_s1_readdata :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal SWITCHES_s1_readdata_from_sa :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal SWITCHES_s1_reset_n :  STD_LOGIC;
                signal TIMER0_s1_address :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal TIMER0_s1_chipselect :  STD_LOGIC;
                signal TIMER0_s1_irq :  STD_LOGIC;
                signal TIMER0_s1_irq_from_sa :  STD_LOGIC;
                signal TIMER0_s1_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal TIMER0_s1_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal TIMER0_s1_reset_n :  STD_LOGIC;
                signal TIMER0_s1_write_n :  STD_LOGIC;
                signal TIMER0_s1_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal VGA_avalon_character_slave_address :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal VGA_avalon_character_slave_chipselect :  STD_LOGIC;
                signal VGA_avalon_character_slave_read :  STD_LOGIC;
                signal VGA_avalon_character_slave_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal VGA_avalon_character_slave_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal VGA_avalon_character_slave_write :  STD_LOGIC;
                signal VGA_avalon_character_slave_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clk_25_reset :  STD_LOGIC;
                signal clk_25_reset_n :  STD_LOGIC;
                signal clk_90_reset :  STD_LOGIC;
                signal clk_90_reset_n :  STD_LOGIC;
                signal clk_reset_n :  STD_LOGIC;
                signal clock_0_in_address :  STD_LOGIC_VECTOR (14 DOWNTO 0);
                signal clock_0_in_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_0_in_endofpacket :  STD_LOGIC;
                signal clock_0_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_0_in_nativeaddress :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal clock_0_in_read :  STD_LOGIC;
                signal clock_0_in_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clock_0_in_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clock_0_in_reset_n :  STD_LOGIC;
                signal clock_0_in_waitrequest :  STD_LOGIC;
                signal clock_0_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_0_in_write :  STD_LOGIC;
                signal clock_0_in_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clock_0_out_address :  STD_LOGIC_VECTOR (14 DOWNTO 0);
                signal clock_0_out_address_to_slave :  STD_LOGIC_VECTOR (14 DOWNTO 0);
                signal clock_0_out_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_0_out_endofpacket :  STD_LOGIC;
                signal clock_0_out_granted_VGA_avalon_character_slave :  STD_LOGIC;
                signal clock_0_out_nativeaddress :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal clock_0_out_qualified_request_VGA_avalon_character_slave :  STD_LOGIC;
                signal clock_0_out_read :  STD_LOGIC;
                signal clock_0_out_read_data_valid_VGA_avalon_character_slave :  STD_LOGIC;
                signal clock_0_out_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clock_0_out_requests_VGA_avalon_character_slave :  STD_LOGIC;
                signal clock_0_out_reset_n :  STD_LOGIC;
                signal clock_0_out_waitrequest :  STD_LOGIC;
                signal clock_0_out_write :  STD_LOGIC;
                signal clock_0_out_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal clock_1_in_address :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_1_in_byteenable :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_endofpacket :  STD_LOGIC;
                signal clock_1_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_1_in_nativeaddress :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal clock_1_in_read :  STD_LOGIC;
                signal clock_1_in_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal clock_1_in_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal clock_1_in_reset_n :  STD_LOGIC;
                signal clock_1_in_waitrequest :  STD_LOGIC;
                signal clock_1_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_1_in_write :  STD_LOGIC;
                signal clock_1_in_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal clock_1_out_address :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_1_out_address_to_slave :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_1_out_byteenable :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_endofpacket :  STD_LOGIC;
                signal clock_1_out_granted_PLL_s1 :  STD_LOGIC;
                signal clock_1_out_nativeaddress :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal clock_1_out_qualified_request_PLL_s1 :  STD_LOGIC;
                signal clock_1_out_read :  STD_LOGIC;
                signal clock_1_out_read_data_valid_PLL_s1 :  STD_LOGIC;
                signal clock_1_out_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal clock_1_out_requests_PLL_s1 :  STD_LOGIC;
                signal clock_1_out_reset_n :  STD_LOGIC;
                signal clock_1_out_waitrequest :  STD_LOGIC;
                signal clock_1_out_write :  STD_LOGIC;
                signal clock_1_out_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal d1_AVALON_avalon_slave_end_xfer :  STD_LOGIC;
                signal d1_CPU_jtag_debug_module_end_xfer :  STD_LOGIC;
                signal d1_IRDA_s1_end_xfer :  STD_LOGIC;
                signal d1_JTAG_avalon_jtag_slave_end_xfer :  STD_LOGIC;
                signal d1_KEYS_s1_end_xfer :  STD_LOGIC;
                signal d1_LCD_control_slave_end_xfer :  STD_LOGIC;
                signal d1_PLL_s1_end_xfer :  STD_LOGIC;
                signal d1_SDRAM_s1_end_xfer :  STD_LOGIC;
                signal d1_SWITCHES_s1_end_xfer :  STD_LOGIC;
                signal d1_TIMER0_s1_end_xfer :  STD_LOGIC;
                signal d1_VGA_avalon_character_slave_end_xfer :  STD_LOGIC;
                signal d1_clock_0_in_end_xfer :  STD_LOGIC;
                signal d1_clock_1_in_end_xfer :  STD_LOGIC;
                signal internal_LCD_E_from_the_LCD :  STD_LOGIC;
                signal internal_LCD_RS_from_the_LCD :  STD_LOGIC;
                signal internal_LCD_RW_from_the_LCD :  STD_LOGIC;
                signal internal_VGA_BLANK_from_the_VGA :  STD_LOGIC;
                signal internal_VGA_B_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_VGA_G_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_VGA_HS_from_the_VGA :  STD_LOGIC;
                signal internal_VGA_R_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_VGA_SYNC_from_the_VGA :  STD_LOGIC;
                signal internal_VGA_VS_from_the_VGA :  STD_LOGIC;
                signal internal_address_from_the_AVALON :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_bus_enable_from_the_AVALON :  STD_LOGIC;
                signal internal_byte_enable_from_the_AVALON :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal internal_clk_25 :  STD_LOGIC;
                signal internal_clk_90 :  STD_LOGIC;
                signal internal_rw_from_the_AVALON :  STD_LOGIC;
                signal internal_txd_from_the_IRDA :  STD_LOGIC;
                signal internal_write_data_from_the_AVALON :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal internal_zs_addr_from_the_SDRAM :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal internal_zs_ba_from_the_SDRAM :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_zs_cas_n_from_the_SDRAM :  STD_LOGIC;
                signal internal_zs_cke_from_the_SDRAM :  STD_LOGIC;
                signal internal_zs_cs_n_from_the_SDRAM :  STD_LOGIC;
                signal internal_zs_dqm_from_the_SDRAM :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_zs_ras_n_from_the_SDRAM :  STD_LOGIC;
                signal internal_zs_we_n_from_the_SDRAM :  STD_LOGIC;
                signal module_input :  STD_LOGIC;
                signal module_input7 :  STD_LOGIC;
                signal module_input8 :  STD_LOGIC;
                signal out_clk_PLL_c0 :  STD_LOGIC;
                signal out_clk_PLL_c1 :  STD_LOGIC;
                signal out_clk_PLL_c2 :  STD_LOGIC;
                signal registered_CPU_data_master_read_data_valid_AVALON_avalon_slave :  STD_LOGIC;
                signal reset_n_sources :  STD_LOGIC;

begin

  --the_AVALON_avalon_slave, which is an e_instance
  the_AVALON_avalon_slave : AVALON_avalon_slave_arbitrator
    port map(
      AVALON_avalon_slave_address => AVALON_avalon_slave_address,
      AVALON_avalon_slave_byteenable => AVALON_avalon_slave_byteenable,
      AVALON_avalon_slave_chipselect => AVALON_avalon_slave_chipselect,
      AVALON_avalon_slave_irq_from_sa => AVALON_avalon_slave_irq_from_sa,
      AVALON_avalon_slave_read => AVALON_avalon_slave_read,
      AVALON_avalon_slave_readdata_from_sa => AVALON_avalon_slave_readdata_from_sa,
      AVALON_avalon_slave_waitrequest_from_sa => AVALON_avalon_slave_waitrequest_from_sa,
      AVALON_avalon_slave_write => AVALON_avalon_slave_write,
      AVALON_avalon_slave_writedata => AVALON_avalon_slave_writedata,
      CPU_data_master_granted_AVALON_avalon_slave => CPU_data_master_granted_AVALON_avalon_slave,
      CPU_data_master_qualified_request_AVALON_avalon_slave => CPU_data_master_qualified_request_AVALON_avalon_slave,
      CPU_data_master_read_data_valid_AVALON_avalon_slave => CPU_data_master_read_data_valid_AVALON_avalon_slave,
      CPU_data_master_requests_AVALON_avalon_slave => CPU_data_master_requests_AVALON_avalon_slave,
      CPU_instruction_master_granted_AVALON_avalon_slave => CPU_instruction_master_granted_AVALON_avalon_slave,
      CPU_instruction_master_qualified_request_AVALON_avalon_slave => CPU_instruction_master_qualified_request_AVALON_avalon_slave,
      CPU_instruction_master_read_data_valid_AVALON_avalon_slave => CPU_instruction_master_read_data_valid_AVALON_avalon_slave,
      CPU_instruction_master_requests_AVALON_avalon_slave => CPU_instruction_master_requests_AVALON_avalon_slave,
      d1_AVALON_avalon_slave_end_xfer => d1_AVALON_avalon_slave_end_xfer,
      registered_CPU_data_master_read_data_valid_AVALON_avalon_slave => registered_CPU_data_master_read_data_valid_AVALON_avalon_slave,
      AVALON_avalon_slave_irq => AVALON_avalon_slave_irq,
      AVALON_avalon_slave_readdata => AVALON_avalon_slave_readdata,
      AVALON_avalon_slave_waitrequest => AVALON_avalon_slave_waitrequest,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      CPU_instruction_master_address_to_slave => CPU_instruction_master_address_to_slave,
      CPU_instruction_master_latency_counter => CPU_instruction_master_latency_counter,
      CPU_instruction_master_read => CPU_instruction_master_read,
      CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register => CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --complemented clk_90_reset_n, which is an e_assign
  clk_90_reset <= NOT clk_90_reset_n;
  --reset is asserted asynchronously and deasserted synchronously
  NIOS_II_reset_clk_90_domain_synch : NIOS_II_reset_clk_90_domain_synch_module
    port map(
      data_out => clk_90_reset_n,
      clk => internal_clk_90,
      data_in => module_input,
      reset_n => reset_n_sources
    );

  module_input <= std_logic'('1');

  --reset sources mux, which is an e_mux
  reset_n_sources <= Vector_To_Std_Logic(NOT (((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT reset_n))) OR std_logic_vector'("00000000000000000000000000000000")) OR std_logic_vector'("00000000000000000000000000000000")) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_jtag_debug_module_resetrequest_from_sa)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(CPU_jtag_debug_module_resetrequest_from_sa)))) OR std_logic_vector'("00000000000000000000000000000000")) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(PLL_s1_resetrequest_from_sa)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(PLL_s1_resetrequest_from_sa))))));
  --the_AVALON, which is an e_ptf_instance
  the_AVALON : AVALON
    port map(
      address => internal_address_from_the_AVALON,
      avalon_irq => AVALON_avalon_slave_irq,
      avalon_readdata => AVALON_avalon_slave_readdata,
      avalon_waitrequest => AVALON_avalon_slave_waitrequest,
      bus_enable => internal_bus_enable_from_the_AVALON,
      byte_enable => internal_byte_enable_from_the_AVALON,
      rw => internal_rw_from_the_AVALON,
      write_data => internal_write_data_from_the_AVALON,
      acknowledge => acknowledge_to_the_AVALON,
      avalon_address => AVALON_avalon_slave_address,
      avalon_byteenable => AVALON_avalon_slave_byteenable,
      avalon_chipselect => AVALON_avalon_slave_chipselect,
      avalon_read => AVALON_avalon_slave_read,
      avalon_write => AVALON_avalon_slave_write,
      avalon_writedata => AVALON_avalon_slave_writedata,
      clk => internal_clk_90,
      irq => irq_to_the_AVALON,
      read_data => read_data_to_the_AVALON,
      reset => clk_90_reset
    );


  --the_CPU_jtag_debug_module, which is an e_instance
  the_CPU_jtag_debug_module : CPU_jtag_debug_module_arbitrator
    port map(
      CPU_data_master_granted_CPU_jtag_debug_module => CPU_data_master_granted_CPU_jtag_debug_module,
      CPU_data_master_qualified_request_CPU_jtag_debug_module => CPU_data_master_qualified_request_CPU_jtag_debug_module,
      CPU_data_master_read_data_valid_CPU_jtag_debug_module => CPU_data_master_read_data_valid_CPU_jtag_debug_module,
      CPU_data_master_requests_CPU_jtag_debug_module => CPU_data_master_requests_CPU_jtag_debug_module,
      CPU_instruction_master_granted_CPU_jtag_debug_module => CPU_instruction_master_granted_CPU_jtag_debug_module,
      CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_qualified_request_CPU_jtag_debug_module,
      CPU_instruction_master_read_data_valid_CPU_jtag_debug_module => CPU_instruction_master_read_data_valid_CPU_jtag_debug_module,
      CPU_instruction_master_requests_CPU_jtag_debug_module => CPU_instruction_master_requests_CPU_jtag_debug_module,
      CPU_jtag_debug_module_address => CPU_jtag_debug_module_address,
      CPU_jtag_debug_module_begintransfer => CPU_jtag_debug_module_begintransfer,
      CPU_jtag_debug_module_byteenable => CPU_jtag_debug_module_byteenable,
      CPU_jtag_debug_module_chipselect => CPU_jtag_debug_module_chipselect,
      CPU_jtag_debug_module_debugaccess => CPU_jtag_debug_module_debugaccess,
      CPU_jtag_debug_module_readdata_from_sa => CPU_jtag_debug_module_readdata_from_sa,
      CPU_jtag_debug_module_reset => CPU_jtag_debug_module_reset,
      CPU_jtag_debug_module_reset_n => CPU_jtag_debug_module_reset_n,
      CPU_jtag_debug_module_resetrequest_from_sa => CPU_jtag_debug_module_resetrequest_from_sa,
      CPU_jtag_debug_module_write => CPU_jtag_debug_module_write,
      CPU_jtag_debug_module_writedata => CPU_jtag_debug_module_writedata,
      d1_CPU_jtag_debug_module_end_xfer => d1_CPU_jtag_debug_module_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_debugaccess => CPU_data_master_debugaccess,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      CPU_instruction_master_address_to_slave => CPU_instruction_master_address_to_slave,
      CPU_instruction_master_latency_counter => CPU_instruction_master_latency_counter,
      CPU_instruction_master_read => CPU_instruction_master_read,
      CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register => CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register,
      CPU_jtag_debug_module_readdata => CPU_jtag_debug_module_readdata,
      CPU_jtag_debug_module_resetrequest => CPU_jtag_debug_module_resetrequest,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_CPU_data_master, which is an e_instance
  the_CPU_data_master : CPU_data_master_arbitrator
    port map(
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_dbs_address => CPU_data_master_dbs_address,
      CPU_data_master_dbs_write_16 => CPU_data_master_dbs_write_16,
      CPU_data_master_irq => CPU_data_master_irq,
      CPU_data_master_no_byte_enables_and_last_term => CPU_data_master_no_byte_enables_and_last_term,
      CPU_data_master_readdata => CPU_data_master_readdata,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      AVALON_avalon_slave_irq_from_sa => AVALON_avalon_slave_irq_from_sa,
      AVALON_avalon_slave_readdata_from_sa => AVALON_avalon_slave_readdata_from_sa,
      AVALON_avalon_slave_waitrequest_from_sa => AVALON_avalon_slave_waitrequest_from_sa,
      CPU_data_master_address => CPU_data_master_address,
      CPU_data_master_byteenable_SDRAM_s1 => CPU_data_master_byteenable_SDRAM_s1,
      CPU_data_master_debugaccess => CPU_data_master_debugaccess,
      CPU_data_master_granted_AVALON_avalon_slave => CPU_data_master_granted_AVALON_avalon_slave,
      CPU_data_master_granted_CPU_jtag_debug_module => CPU_data_master_granted_CPU_jtag_debug_module,
      CPU_data_master_granted_IRDA_s1 => CPU_data_master_granted_IRDA_s1,
      CPU_data_master_granted_JTAG_avalon_jtag_slave => CPU_data_master_granted_JTAG_avalon_jtag_slave,
      CPU_data_master_granted_KEYS_s1 => CPU_data_master_granted_KEYS_s1,
      CPU_data_master_granted_LCD_control_slave => CPU_data_master_granted_LCD_control_slave,
      CPU_data_master_granted_SDRAM_s1 => CPU_data_master_granted_SDRAM_s1,
      CPU_data_master_granted_SWITCHES_s1 => CPU_data_master_granted_SWITCHES_s1,
      CPU_data_master_granted_TIMER0_s1 => CPU_data_master_granted_TIMER0_s1,
      CPU_data_master_granted_clock_0_in => CPU_data_master_granted_clock_0_in,
      CPU_data_master_granted_clock_1_in => CPU_data_master_granted_clock_1_in,
      CPU_data_master_qualified_request_AVALON_avalon_slave => CPU_data_master_qualified_request_AVALON_avalon_slave,
      CPU_data_master_qualified_request_CPU_jtag_debug_module => CPU_data_master_qualified_request_CPU_jtag_debug_module,
      CPU_data_master_qualified_request_IRDA_s1 => CPU_data_master_qualified_request_IRDA_s1,
      CPU_data_master_qualified_request_JTAG_avalon_jtag_slave => CPU_data_master_qualified_request_JTAG_avalon_jtag_slave,
      CPU_data_master_qualified_request_KEYS_s1 => CPU_data_master_qualified_request_KEYS_s1,
      CPU_data_master_qualified_request_LCD_control_slave => CPU_data_master_qualified_request_LCD_control_slave,
      CPU_data_master_qualified_request_SDRAM_s1 => CPU_data_master_qualified_request_SDRAM_s1,
      CPU_data_master_qualified_request_SWITCHES_s1 => CPU_data_master_qualified_request_SWITCHES_s1,
      CPU_data_master_qualified_request_TIMER0_s1 => CPU_data_master_qualified_request_TIMER0_s1,
      CPU_data_master_qualified_request_clock_0_in => CPU_data_master_qualified_request_clock_0_in,
      CPU_data_master_qualified_request_clock_1_in => CPU_data_master_qualified_request_clock_1_in,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_read_data_valid_AVALON_avalon_slave => CPU_data_master_read_data_valid_AVALON_avalon_slave,
      CPU_data_master_read_data_valid_CPU_jtag_debug_module => CPU_data_master_read_data_valid_CPU_jtag_debug_module,
      CPU_data_master_read_data_valid_IRDA_s1 => CPU_data_master_read_data_valid_IRDA_s1,
      CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave => CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave,
      CPU_data_master_read_data_valid_KEYS_s1 => CPU_data_master_read_data_valid_KEYS_s1,
      CPU_data_master_read_data_valid_LCD_control_slave => CPU_data_master_read_data_valid_LCD_control_slave,
      CPU_data_master_read_data_valid_SDRAM_s1 => CPU_data_master_read_data_valid_SDRAM_s1,
      CPU_data_master_read_data_valid_SDRAM_s1_shift_register => CPU_data_master_read_data_valid_SDRAM_s1_shift_register,
      CPU_data_master_read_data_valid_SWITCHES_s1 => CPU_data_master_read_data_valid_SWITCHES_s1,
      CPU_data_master_read_data_valid_TIMER0_s1 => CPU_data_master_read_data_valid_TIMER0_s1,
      CPU_data_master_read_data_valid_clock_0_in => CPU_data_master_read_data_valid_clock_0_in,
      CPU_data_master_read_data_valid_clock_1_in => CPU_data_master_read_data_valid_clock_1_in,
      CPU_data_master_requests_AVALON_avalon_slave => CPU_data_master_requests_AVALON_avalon_slave,
      CPU_data_master_requests_CPU_jtag_debug_module => CPU_data_master_requests_CPU_jtag_debug_module,
      CPU_data_master_requests_IRDA_s1 => CPU_data_master_requests_IRDA_s1,
      CPU_data_master_requests_JTAG_avalon_jtag_slave => CPU_data_master_requests_JTAG_avalon_jtag_slave,
      CPU_data_master_requests_KEYS_s1 => CPU_data_master_requests_KEYS_s1,
      CPU_data_master_requests_LCD_control_slave => CPU_data_master_requests_LCD_control_slave,
      CPU_data_master_requests_SDRAM_s1 => CPU_data_master_requests_SDRAM_s1,
      CPU_data_master_requests_SWITCHES_s1 => CPU_data_master_requests_SWITCHES_s1,
      CPU_data_master_requests_TIMER0_s1 => CPU_data_master_requests_TIMER0_s1,
      CPU_data_master_requests_clock_0_in => CPU_data_master_requests_clock_0_in,
      CPU_data_master_requests_clock_1_in => CPU_data_master_requests_clock_1_in,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      CPU_jtag_debug_module_readdata_from_sa => CPU_jtag_debug_module_readdata_from_sa,
      IRDA_s1_irq_from_sa => IRDA_s1_irq_from_sa,
      IRDA_s1_readdata_from_sa => IRDA_s1_readdata_from_sa,
      JTAG_avalon_jtag_slave_irq_from_sa => JTAG_avalon_jtag_slave_irq_from_sa,
      JTAG_avalon_jtag_slave_readdata_from_sa => JTAG_avalon_jtag_slave_readdata_from_sa,
      JTAG_avalon_jtag_slave_waitrequest_from_sa => JTAG_avalon_jtag_slave_waitrequest_from_sa,
      KEYS_s1_readdata_from_sa => KEYS_s1_readdata_from_sa,
      LCD_control_slave_readdata_from_sa => LCD_control_slave_readdata_from_sa,
      LCD_control_slave_wait_counter_eq_0 => LCD_control_slave_wait_counter_eq_0,
      LCD_control_slave_wait_counter_eq_1 => LCD_control_slave_wait_counter_eq_1,
      SDRAM_s1_readdata_from_sa => SDRAM_s1_readdata_from_sa,
      SDRAM_s1_waitrequest_from_sa => SDRAM_s1_waitrequest_from_sa,
      SWITCHES_s1_readdata_from_sa => SWITCHES_s1_readdata_from_sa,
      TIMER0_s1_irq_from_sa => TIMER0_s1_irq_from_sa,
      TIMER0_s1_readdata_from_sa => TIMER0_s1_readdata_from_sa,
      clk => internal_clk_90,
      clock_0_in_readdata_from_sa => clock_0_in_readdata_from_sa,
      clock_0_in_waitrequest_from_sa => clock_0_in_waitrequest_from_sa,
      clock_1_in_readdata_from_sa => clock_1_in_readdata_from_sa,
      clock_1_in_waitrequest_from_sa => clock_1_in_waitrequest_from_sa,
      d1_AVALON_avalon_slave_end_xfer => d1_AVALON_avalon_slave_end_xfer,
      d1_CPU_jtag_debug_module_end_xfer => d1_CPU_jtag_debug_module_end_xfer,
      d1_IRDA_s1_end_xfer => d1_IRDA_s1_end_xfer,
      d1_JTAG_avalon_jtag_slave_end_xfer => d1_JTAG_avalon_jtag_slave_end_xfer,
      d1_KEYS_s1_end_xfer => d1_KEYS_s1_end_xfer,
      d1_LCD_control_slave_end_xfer => d1_LCD_control_slave_end_xfer,
      d1_SDRAM_s1_end_xfer => d1_SDRAM_s1_end_xfer,
      d1_SWITCHES_s1_end_xfer => d1_SWITCHES_s1_end_xfer,
      d1_TIMER0_s1_end_xfer => d1_TIMER0_s1_end_xfer,
      d1_clock_0_in_end_xfer => d1_clock_0_in_end_xfer,
      d1_clock_1_in_end_xfer => d1_clock_1_in_end_xfer,
      registered_CPU_data_master_read_data_valid_AVALON_avalon_slave => registered_CPU_data_master_read_data_valid_AVALON_avalon_slave,
      reset_n => clk_90_reset_n
    );


  --the_CPU_instruction_master, which is an e_instance
  the_CPU_instruction_master : CPU_instruction_master_arbitrator
    port map(
      CPU_instruction_master_address_to_slave => CPU_instruction_master_address_to_slave,
      CPU_instruction_master_dbs_address => CPU_instruction_master_dbs_address,
      CPU_instruction_master_latency_counter => CPU_instruction_master_latency_counter,
      CPU_instruction_master_readdata => CPU_instruction_master_readdata,
      CPU_instruction_master_readdatavalid => CPU_instruction_master_readdatavalid,
      CPU_instruction_master_waitrequest => CPU_instruction_master_waitrequest,
      AVALON_avalon_slave_readdata_from_sa => AVALON_avalon_slave_readdata_from_sa,
      AVALON_avalon_slave_waitrequest_from_sa => AVALON_avalon_slave_waitrequest_from_sa,
      CPU_instruction_master_address => CPU_instruction_master_address,
      CPU_instruction_master_granted_AVALON_avalon_slave => CPU_instruction_master_granted_AVALON_avalon_slave,
      CPU_instruction_master_granted_CPU_jtag_debug_module => CPU_instruction_master_granted_CPU_jtag_debug_module,
      CPU_instruction_master_granted_SDRAM_s1 => CPU_instruction_master_granted_SDRAM_s1,
      CPU_instruction_master_qualified_request_AVALON_avalon_slave => CPU_instruction_master_qualified_request_AVALON_avalon_slave,
      CPU_instruction_master_qualified_request_CPU_jtag_debug_module => CPU_instruction_master_qualified_request_CPU_jtag_debug_module,
      CPU_instruction_master_qualified_request_SDRAM_s1 => CPU_instruction_master_qualified_request_SDRAM_s1,
      CPU_instruction_master_read => CPU_instruction_master_read,
      CPU_instruction_master_read_data_valid_AVALON_avalon_slave => CPU_instruction_master_read_data_valid_AVALON_avalon_slave,
      CPU_instruction_master_read_data_valid_CPU_jtag_debug_module => CPU_instruction_master_read_data_valid_CPU_jtag_debug_module,
      CPU_instruction_master_read_data_valid_SDRAM_s1 => CPU_instruction_master_read_data_valid_SDRAM_s1,
      CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register => CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register,
      CPU_instruction_master_requests_AVALON_avalon_slave => CPU_instruction_master_requests_AVALON_avalon_slave,
      CPU_instruction_master_requests_CPU_jtag_debug_module => CPU_instruction_master_requests_CPU_jtag_debug_module,
      CPU_instruction_master_requests_SDRAM_s1 => CPU_instruction_master_requests_SDRAM_s1,
      CPU_jtag_debug_module_readdata_from_sa => CPU_jtag_debug_module_readdata_from_sa,
      SDRAM_s1_readdata_from_sa => SDRAM_s1_readdata_from_sa,
      SDRAM_s1_waitrequest_from_sa => SDRAM_s1_waitrequest_from_sa,
      clk => internal_clk_90,
      d1_AVALON_avalon_slave_end_xfer => d1_AVALON_avalon_slave_end_xfer,
      d1_CPU_jtag_debug_module_end_xfer => d1_CPU_jtag_debug_module_end_xfer,
      d1_SDRAM_s1_end_xfer => d1_SDRAM_s1_end_xfer,
      reset_n => clk_90_reset_n
    );


  --the_CPU, which is an e_ptf_instance
  the_CPU : CPU
    port map(
      d_address => CPU_data_master_address,
      d_byteenable => CPU_data_master_byteenable,
      d_read => CPU_data_master_read,
      d_write => CPU_data_master_write,
      d_writedata => CPU_data_master_writedata,
      i_address => CPU_instruction_master_address,
      i_read => CPU_instruction_master_read,
      jtag_debug_module_debugaccess_to_roms => CPU_data_master_debugaccess,
      jtag_debug_module_readdata => CPU_jtag_debug_module_readdata,
      jtag_debug_module_resetrequest => CPU_jtag_debug_module_resetrequest,
      clk => internal_clk_90,
      d_irq => CPU_data_master_irq,
      d_readdata => CPU_data_master_readdata,
      d_waitrequest => CPU_data_master_waitrequest,
      i_readdata => CPU_instruction_master_readdata,
      i_readdatavalid => CPU_instruction_master_readdatavalid,
      i_waitrequest => CPU_instruction_master_waitrequest,
      jtag_debug_module_address => CPU_jtag_debug_module_address,
      jtag_debug_module_begintransfer => CPU_jtag_debug_module_begintransfer,
      jtag_debug_module_byteenable => CPU_jtag_debug_module_byteenable,
      jtag_debug_module_clk => internal_clk_90,
      jtag_debug_module_debugaccess => CPU_jtag_debug_module_debugaccess,
      jtag_debug_module_reset => CPU_jtag_debug_module_reset,
      jtag_debug_module_select => CPU_jtag_debug_module_chipselect,
      jtag_debug_module_write => CPU_jtag_debug_module_write,
      jtag_debug_module_writedata => CPU_jtag_debug_module_writedata,
      reset_n => CPU_jtag_debug_module_reset_n
    );


  --the_IRDA_s1, which is an e_instance
  the_IRDA_s1 : IRDA_s1_arbitrator
    port map(
      CPU_data_master_granted_IRDA_s1 => CPU_data_master_granted_IRDA_s1,
      CPU_data_master_qualified_request_IRDA_s1 => CPU_data_master_qualified_request_IRDA_s1,
      CPU_data_master_read_data_valid_IRDA_s1 => CPU_data_master_read_data_valid_IRDA_s1,
      CPU_data_master_requests_IRDA_s1 => CPU_data_master_requests_IRDA_s1,
      IRDA_s1_address => IRDA_s1_address,
      IRDA_s1_begintransfer => IRDA_s1_begintransfer,
      IRDA_s1_chipselect => IRDA_s1_chipselect,
      IRDA_s1_dataavailable_from_sa => IRDA_s1_dataavailable_from_sa,
      IRDA_s1_irq_from_sa => IRDA_s1_irq_from_sa,
      IRDA_s1_read_n => IRDA_s1_read_n,
      IRDA_s1_readdata_from_sa => IRDA_s1_readdata_from_sa,
      IRDA_s1_readyfordata_from_sa => IRDA_s1_readyfordata_from_sa,
      IRDA_s1_reset_n => IRDA_s1_reset_n,
      IRDA_s1_write_n => IRDA_s1_write_n,
      IRDA_s1_writedata => IRDA_s1_writedata,
      d1_IRDA_s1_end_xfer => d1_IRDA_s1_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      IRDA_s1_dataavailable => IRDA_s1_dataavailable,
      IRDA_s1_irq => IRDA_s1_irq,
      IRDA_s1_readdata => IRDA_s1_readdata,
      IRDA_s1_readyfordata => IRDA_s1_readyfordata,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_IRDA, which is an e_ptf_instance
  the_IRDA : IRDA
    port map(
      dataavailable => IRDA_s1_dataavailable,
      irq => IRDA_s1_irq,
      readdata => IRDA_s1_readdata,
      readyfordata => IRDA_s1_readyfordata,
      txd => internal_txd_from_the_IRDA,
      address => IRDA_s1_address,
      begintransfer => IRDA_s1_begintransfer,
      chipselect => IRDA_s1_chipselect,
      clk => internal_clk_90,
      read_n => IRDA_s1_read_n,
      reset_n => IRDA_s1_reset_n,
      rxd => rxd_to_the_IRDA,
      write_n => IRDA_s1_write_n,
      writedata => IRDA_s1_writedata
    );


  --the_JTAG_avalon_jtag_slave, which is an e_instance
  the_JTAG_avalon_jtag_slave : JTAG_avalon_jtag_slave_arbitrator
    port map(
      CPU_data_master_granted_JTAG_avalon_jtag_slave => CPU_data_master_granted_JTAG_avalon_jtag_slave,
      CPU_data_master_qualified_request_JTAG_avalon_jtag_slave => CPU_data_master_qualified_request_JTAG_avalon_jtag_slave,
      CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave => CPU_data_master_read_data_valid_JTAG_avalon_jtag_slave,
      CPU_data_master_requests_JTAG_avalon_jtag_slave => CPU_data_master_requests_JTAG_avalon_jtag_slave,
      JTAG_avalon_jtag_slave_address => JTAG_avalon_jtag_slave_address,
      JTAG_avalon_jtag_slave_chipselect => JTAG_avalon_jtag_slave_chipselect,
      JTAG_avalon_jtag_slave_dataavailable_from_sa => JTAG_avalon_jtag_slave_dataavailable_from_sa,
      JTAG_avalon_jtag_slave_irq_from_sa => JTAG_avalon_jtag_slave_irq_from_sa,
      JTAG_avalon_jtag_slave_read_n => JTAG_avalon_jtag_slave_read_n,
      JTAG_avalon_jtag_slave_readdata_from_sa => JTAG_avalon_jtag_slave_readdata_from_sa,
      JTAG_avalon_jtag_slave_readyfordata_from_sa => JTAG_avalon_jtag_slave_readyfordata_from_sa,
      JTAG_avalon_jtag_slave_reset_n => JTAG_avalon_jtag_slave_reset_n,
      JTAG_avalon_jtag_slave_waitrequest_from_sa => JTAG_avalon_jtag_slave_waitrequest_from_sa,
      JTAG_avalon_jtag_slave_write_n => JTAG_avalon_jtag_slave_write_n,
      JTAG_avalon_jtag_slave_writedata => JTAG_avalon_jtag_slave_writedata,
      d1_JTAG_avalon_jtag_slave_end_xfer => d1_JTAG_avalon_jtag_slave_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      JTAG_avalon_jtag_slave_dataavailable => JTAG_avalon_jtag_slave_dataavailable,
      JTAG_avalon_jtag_slave_irq => JTAG_avalon_jtag_slave_irq,
      JTAG_avalon_jtag_slave_readdata => JTAG_avalon_jtag_slave_readdata,
      JTAG_avalon_jtag_slave_readyfordata => JTAG_avalon_jtag_slave_readyfordata,
      JTAG_avalon_jtag_slave_waitrequest => JTAG_avalon_jtag_slave_waitrequest,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_JTAG, which is an e_ptf_instance
  the_JTAG : JTAG
    port map(
      av_irq => JTAG_avalon_jtag_slave_irq,
      av_readdata => JTAG_avalon_jtag_slave_readdata,
      av_waitrequest => JTAG_avalon_jtag_slave_waitrequest,
      dataavailable => JTAG_avalon_jtag_slave_dataavailable,
      readyfordata => JTAG_avalon_jtag_slave_readyfordata,
      av_address => JTAG_avalon_jtag_slave_address,
      av_chipselect => JTAG_avalon_jtag_slave_chipselect,
      av_read_n => JTAG_avalon_jtag_slave_read_n,
      av_write_n => JTAG_avalon_jtag_slave_write_n,
      av_writedata => JTAG_avalon_jtag_slave_writedata,
      clk => internal_clk_90,
      rst_n => JTAG_avalon_jtag_slave_reset_n
    );


  --the_KEYS_s1, which is an e_instance
  the_KEYS_s1 : KEYS_s1_arbitrator
    port map(
      CPU_data_master_granted_KEYS_s1 => CPU_data_master_granted_KEYS_s1,
      CPU_data_master_qualified_request_KEYS_s1 => CPU_data_master_qualified_request_KEYS_s1,
      CPU_data_master_read_data_valid_KEYS_s1 => CPU_data_master_read_data_valid_KEYS_s1,
      CPU_data_master_requests_KEYS_s1 => CPU_data_master_requests_KEYS_s1,
      KEYS_s1_address => KEYS_s1_address,
      KEYS_s1_chipselect => KEYS_s1_chipselect,
      KEYS_s1_readdata_from_sa => KEYS_s1_readdata_from_sa,
      KEYS_s1_reset_n => KEYS_s1_reset_n,
      KEYS_s1_write_n => KEYS_s1_write_n,
      KEYS_s1_writedata => KEYS_s1_writedata,
      d1_KEYS_s1_end_xfer => d1_KEYS_s1_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      KEYS_s1_readdata => KEYS_s1_readdata,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_KEYS, which is an e_ptf_instance
  the_KEYS : KEYS
    port map(
      irq => KEYS_s1_irq,
      readdata => KEYS_s1_readdata,
      address => KEYS_s1_address,
      chipselect => KEYS_s1_chipselect,
      clk => internal_clk_90,
      in_port => in_port_to_the_KEYS,
      reset_n => KEYS_s1_reset_n,
      write_n => KEYS_s1_write_n,
      writedata => KEYS_s1_writedata
    );


  --the_LCD_control_slave, which is an e_instance
  the_LCD_control_slave : LCD_control_slave_arbitrator
    port map(
      CPU_data_master_granted_LCD_control_slave => CPU_data_master_granted_LCD_control_slave,
      CPU_data_master_qualified_request_LCD_control_slave => CPU_data_master_qualified_request_LCD_control_slave,
      CPU_data_master_read_data_valid_LCD_control_slave => CPU_data_master_read_data_valid_LCD_control_slave,
      CPU_data_master_requests_LCD_control_slave => CPU_data_master_requests_LCD_control_slave,
      LCD_control_slave_address => LCD_control_slave_address,
      LCD_control_slave_begintransfer => LCD_control_slave_begintransfer,
      LCD_control_slave_read => LCD_control_slave_read,
      LCD_control_slave_readdata_from_sa => LCD_control_slave_readdata_from_sa,
      LCD_control_slave_wait_counter_eq_0 => LCD_control_slave_wait_counter_eq_0,
      LCD_control_slave_wait_counter_eq_1 => LCD_control_slave_wait_counter_eq_1,
      LCD_control_slave_write => LCD_control_slave_write,
      LCD_control_slave_writedata => LCD_control_slave_writedata,
      d1_LCD_control_slave_end_xfer => d1_LCD_control_slave_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      LCD_control_slave_readdata => LCD_control_slave_readdata,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_LCD, which is an e_ptf_instance
  the_LCD : LCD
    port map(
      LCD_E => internal_LCD_E_from_the_LCD,
      LCD_RS => internal_LCD_RS_from_the_LCD,
      LCD_RW => internal_LCD_RW_from_the_LCD,
      LCD_data => LCD_data_to_and_from_the_LCD,
      irq => LCD_control_slave_irq,
      readdata => LCD_control_slave_readdata,
      address => LCD_control_slave_address,
      begintransfer => LCD_control_slave_begintransfer,
      read => LCD_control_slave_read,
      write => LCD_control_slave_write,
      writedata => LCD_control_slave_writedata
    );


  --the_PLL_s1, which is an e_instance
  the_PLL_s1 : PLL_s1_arbitrator
    port map(
      PLL_s1_address => PLL_s1_address,
      PLL_s1_chipselect => PLL_s1_chipselect,
      PLL_s1_read => PLL_s1_read,
      PLL_s1_readdata_from_sa => PLL_s1_readdata_from_sa,
      PLL_s1_reset_n => PLL_s1_reset_n,
      PLL_s1_resetrequest_from_sa => PLL_s1_resetrequest_from_sa,
      PLL_s1_write => PLL_s1_write,
      PLL_s1_writedata => PLL_s1_writedata,
      clock_1_out_granted_PLL_s1 => clock_1_out_granted_PLL_s1,
      clock_1_out_qualified_request_PLL_s1 => clock_1_out_qualified_request_PLL_s1,
      clock_1_out_read_data_valid_PLL_s1 => clock_1_out_read_data_valid_PLL_s1,
      clock_1_out_requests_PLL_s1 => clock_1_out_requests_PLL_s1,
      d1_PLL_s1_end_xfer => d1_PLL_s1_end_xfer,
      PLL_s1_readdata => PLL_s1_readdata,
      PLL_s1_resetrequest => PLL_s1_resetrequest,
      clk => clk,
      clock_1_out_address_to_slave => clock_1_out_address_to_slave,
      clock_1_out_nativeaddress => clock_1_out_nativeaddress,
      clock_1_out_read => clock_1_out_read,
      clock_1_out_write => clock_1_out_write,
      clock_1_out_writedata => clock_1_out_writedata,
      reset_n => clk_reset_n
    );


  --the_PLL, which is an e_ptf_instance
  the_PLL : PLL
    port map(
      c0 => out_clk_PLL_c0,
      c1 => out_clk_PLL_c1,
      c2 => out_clk_PLL_c2,
      readdata => PLL_s1_readdata,
      resetrequest => PLL_s1_resetrequest,
      address => PLL_s1_address,
      chipselect => PLL_s1_chipselect,
      clk => clk,
      read => PLL_s1_read,
      reset_n => PLL_s1_reset_n,
      write => PLL_s1_write,
      writedata => PLL_s1_writedata
    );


  --the_SDRAM_s1, which is an e_instance
  the_SDRAM_s1 : SDRAM_s1_arbitrator
    port map(
      CPU_data_master_byteenable_SDRAM_s1 => CPU_data_master_byteenable_SDRAM_s1,
      CPU_data_master_granted_SDRAM_s1 => CPU_data_master_granted_SDRAM_s1,
      CPU_data_master_qualified_request_SDRAM_s1 => CPU_data_master_qualified_request_SDRAM_s1,
      CPU_data_master_read_data_valid_SDRAM_s1 => CPU_data_master_read_data_valid_SDRAM_s1,
      CPU_data_master_read_data_valid_SDRAM_s1_shift_register => CPU_data_master_read_data_valid_SDRAM_s1_shift_register,
      CPU_data_master_requests_SDRAM_s1 => CPU_data_master_requests_SDRAM_s1,
      CPU_instruction_master_granted_SDRAM_s1 => CPU_instruction_master_granted_SDRAM_s1,
      CPU_instruction_master_qualified_request_SDRAM_s1 => CPU_instruction_master_qualified_request_SDRAM_s1,
      CPU_instruction_master_read_data_valid_SDRAM_s1 => CPU_instruction_master_read_data_valid_SDRAM_s1,
      CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register => CPU_instruction_master_read_data_valid_SDRAM_s1_shift_register,
      CPU_instruction_master_requests_SDRAM_s1 => CPU_instruction_master_requests_SDRAM_s1,
      SDRAM_s1_address => SDRAM_s1_address,
      SDRAM_s1_byteenable_n => SDRAM_s1_byteenable_n,
      SDRAM_s1_chipselect => SDRAM_s1_chipselect,
      SDRAM_s1_read_n => SDRAM_s1_read_n,
      SDRAM_s1_readdata_from_sa => SDRAM_s1_readdata_from_sa,
      SDRAM_s1_reset_n => SDRAM_s1_reset_n,
      SDRAM_s1_waitrequest_from_sa => SDRAM_s1_waitrequest_from_sa,
      SDRAM_s1_write_n => SDRAM_s1_write_n,
      SDRAM_s1_writedata => SDRAM_s1_writedata,
      d1_SDRAM_s1_end_xfer => d1_SDRAM_s1_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_dbs_address => CPU_data_master_dbs_address,
      CPU_data_master_dbs_write_16 => CPU_data_master_dbs_write_16,
      CPU_data_master_no_byte_enables_and_last_term => CPU_data_master_no_byte_enables_and_last_term,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_instruction_master_address_to_slave => CPU_instruction_master_address_to_slave,
      CPU_instruction_master_dbs_address => CPU_instruction_master_dbs_address,
      CPU_instruction_master_latency_counter => CPU_instruction_master_latency_counter,
      CPU_instruction_master_read => CPU_instruction_master_read,
      SDRAM_s1_readdata => SDRAM_s1_readdata,
      SDRAM_s1_readdatavalid => SDRAM_s1_readdatavalid,
      SDRAM_s1_waitrequest => SDRAM_s1_waitrequest,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_SDRAM, which is an e_ptf_instance
  the_SDRAM : SDRAM
    port map(
      za_data => SDRAM_s1_readdata,
      za_valid => SDRAM_s1_readdatavalid,
      za_waitrequest => SDRAM_s1_waitrequest,
      zs_addr => internal_zs_addr_from_the_SDRAM,
      zs_ba => internal_zs_ba_from_the_SDRAM,
      zs_cas_n => internal_zs_cas_n_from_the_SDRAM,
      zs_cke => internal_zs_cke_from_the_SDRAM,
      zs_cs_n => internal_zs_cs_n_from_the_SDRAM,
      zs_dq => zs_dq_to_and_from_the_SDRAM,
      zs_dqm => internal_zs_dqm_from_the_SDRAM,
      zs_ras_n => internal_zs_ras_n_from_the_SDRAM,
      zs_we_n => internal_zs_we_n_from_the_SDRAM,
      az_addr => SDRAM_s1_address,
      az_be_n => SDRAM_s1_byteenable_n,
      az_cs => SDRAM_s1_chipselect,
      az_data => SDRAM_s1_writedata,
      az_rd_n => SDRAM_s1_read_n,
      az_wr_n => SDRAM_s1_write_n,
      clk => internal_clk_90,
      reset_n => SDRAM_s1_reset_n
    );


  --the_SWITCHES_s1, which is an e_instance
  the_SWITCHES_s1 : SWITCHES_s1_arbitrator
    port map(
      CPU_data_master_granted_SWITCHES_s1 => CPU_data_master_granted_SWITCHES_s1,
      CPU_data_master_qualified_request_SWITCHES_s1 => CPU_data_master_qualified_request_SWITCHES_s1,
      CPU_data_master_read_data_valid_SWITCHES_s1 => CPU_data_master_read_data_valid_SWITCHES_s1,
      CPU_data_master_requests_SWITCHES_s1 => CPU_data_master_requests_SWITCHES_s1,
      SWITCHES_s1_address => SWITCHES_s1_address,
      SWITCHES_s1_readdata_from_sa => SWITCHES_s1_readdata_from_sa,
      SWITCHES_s1_reset_n => SWITCHES_s1_reset_n,
      d1_SWITCHES_s1_end_xfer => d1_SWITCHES_s1_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_write => CPU_data_master_write,
      SWITCHES_s1_readdata => SWITCHES_s1_readdata,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_SWITCHES, which is an e_ptf_instance
  the_SWITCHES : SWITCHES
    port map(
      readdata => SWITCHES_s1_readdata,
      address => SWITCHES_s1_address,
      clk => internal_clk_90,
      in_port => in_port_to_the_SWITCHES,
      reset_n => SWITCHES_s1_reset_n
    );


  --the_TIMER0_s1, which is an e_instance
  the_TIMER0_s1 : TIMER0_s1_arbitrator
    port map(
      CPU_data_master_granted_TIMER0_s1 => CPU_data_master_granted_TIMER0_s1,
      CPU_data_master_qualified_request_TIMER0_s1 => CPU_data_master_qualified_request_TIMER0_s1,
      CPU_data_master_read_data_valid_TIMER0_s1 => CPU_data_master_read_data_valid_TIMER0_s1,
      CPU_data_master_requests_TIMER0_s1 => CPU_data_master_requests_TIMER0_s1,
      TIMER0_s1_address => TIMER0_s1_address,
      TIMER0_s1_chipselect => TIMER0_s1_chipselect,
      TIMER0_s1_irq_from_sa => TIMER0_s1_irq_from_sa,
      TIMER0_s1_readdata_from_sa => TIMER0_s1_readdata_from_sa,
      TIMER0_s1_reset_n => TIMER0_s1_reset_n,
      TIMER0_s1_write_n => TIMER0_s1_write_n,
      TIMER0_s1_writedata => TIMER0_s1_writedata,
      d1_TIMER0_s1_end_xfer => d1_TIMER0_s1_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      TIMER0_s1_irq => TIMER0_s1_irq,
      TIMER0_s1_readdata => TIMER0_s1_readdata,
      clk => internal_clk_90,
      reset_n => clk_90_reset_n
    );


  --the_TIMER0, which is an e_ptf_instance
  the_TIMER0 : TIMER0
    port map(
      irq => TIMER0_s1_irq,
      readdata => TIMER0_s1_readdata,
      address => TIMER0_s1_address,
      chipselect => TIMER0_s1_chipselect,
      clk => internal_clk_90,
      reset_n => TIMER0_s1_reset_n,
      write_n => TIMER0_s1_write_n,
      writedata => TIMER0_s1_writedata
    );


  --the_VGA_avalon_character_slave, which is an e_instance
  the_VGA_avalon_character_slave : VGA_avalon_character_slave_arbitrator
    port map(
      VGA_avalon_character_slave_address => VGA_avalon_character_slave_address,
      VGA_avalon_character_slave_chipselect => VGA_avalon_character_slave_chipselect,
      VGA_avalon_character_slave_read => VGA_avalon_character_slave_read,
      VGA_avalon_character_slave_readdata_from_sa => VGA_avalon_character_slave_readdata_from_sa,
      VGA_avalon_character_slave_write => VGA_avalon_character_slave_write,
      VGA_avalon_character_slave_writedata => VGA_avalon_character_slave_writedata,
      clock_0_out_granted_VGA_avalon_character_slave => clock_0_out_granted_VGA_avalon_character_slave,
      clock_0_out_qualified_request_VGA_avalon_character_slave => clock_0_out_qualified_request_VGA_avalon_character_slave,
      clock_0_out_read_data_valid_VGA_avalon_character_slave => clock_0_out_read_data_valid_VGA_avalon_character_slave,
      clock_0_out_requests_VGA_avalon_character_slave => clock_0_out_requests_VGA_avalon_character_slave,
      d1_VGA_avalon_character_slave_end_xfer => d1_VGA_avalon_character_slave_end_xfer,
      VGA_avalon_character_slave_readdata => VGA_avalon_character_slave_readdata,
      clk => clk,
      clock_0_out_address_to_slave => clock_0_out_address_to_slave,
      clock_0_out_read => clock_0_out_read,
      clock_0_out_write => clock_0_out_write,
      clock_0_out_writedata => clock_0_out_writedata,
      reset_n => clk_reset_n
    );


  --complemented clk_25_reset_n, which is an e_assign
  clk_25_reset <= NOT clk_25_reset_n;
  --reset is asserted asynchronously and deasserted synchronously
  NIOS_II_reset_clk_25_domain_synch : NIOS_II_reset_clk_25_domain_synch_module
    port map(
      data_out => clk_25_reset_n,
      clk => internal_clk_25,
      data_in => module_input7,
      reset_n => reset_n_sources
    );

  module_input7 <= std_logic'('1');

  --the_VGA, which is an e_ptf_instance
  the_VGA : VGA
    port map(
      VGA_B => internal_VGA_B_from_the_VGA,
      VGA_BLANK => internal_VGA_BLANK_from_the_VGA,
      VGA_G => internal_VGA_G_from_the_VGA,
      VGA_HS => internal_VGA_HS_from_the_VGA,
      VGA_R => internal_VGA_R_from_the_VGA,
      VGA_SYNC => internal_VGA_SYNC_from_the_VGA,
      VGA_VS => internal_VGA_VS_from_the_VGA,
      char_readdata => VGA_avalon_character_slave_readdata,
      char_address => VGA_avalon_character_slave_address,
      char_chipselect => VGA_avalon_character_slave_chipselect,
      char_clk => clk,
      char_read => VGA_avalon_character_slave_read,
      char_write => VGA_avalon_character_slave_write,
      char_writedata => VGA_avalon_character_slave_writedata,
      reset => clk_25_reset,
      vga_dac_clk => internal_clk_25
    );


  --the_clock_0_in, which is an e_instance
  the_clock_0_in : clock_0_in_arbitrator
    port map(
      CPU_data_master_granted_clock_0_in => CPU_data_master_granted_clock_0_in,
      CPU_data_master_qualified_request_clock_0_in => CPU_data_master_qualified_request_clock_0_in,
      CPU_data_master_read_data_valid_clock_0_in => CPU_data_master_read_data_valid_clock_0_in,
      CPU_data_master_requests_clock_0_in => CPU_data_master_requests_clock_0_in,
      clock_0_in_address => clock_0_in_address,
      clock_0_in_byteenable => clock_0_in_byteenable,
      clock_0_in_endofpacket_from_sa => clock_0_in_endofpacket_from_sa,
      clock_0_in_nativeaddress => clock_0_in_nativeaddress,
      clock_0_in_read => clock_0_in_read,
      clock_0_in_readdata_from_sa => clock_0_in_readdata_from_sa,
      clock_0_in_reset_n => clock_0_in_reset_n,
      clock_0_in_waitrequest_from_sa => clock_0_in_waitrequest_from_sa,
      clock_0_in_write => clock_0_in_write,
      clock_0_in_writedata => clock_0_in_writedata,
      d1_clock_0_in_end_xfer => d1_clock_0_in_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      clk => internal_clk_90,
      clock_0_in_endofpacket => clock_0_in_endofpacket,
      clock_0_in_readdata => clock_0_in_readdata,
      clock_0_in_waitrequest => clock_0_in_waitrequest,
      reset_n => clk_90_reset_n
    );


  --the_clock_0_out, which is an e_instance
  the_clock_0_out : clock_0_out_arbitrator
    port map(
      clock_0_out_address_to_slave => clock_0_out_address_to_slave,
      clock_0_out_readdata => clock_0_out_readdata,
      clock_0_out_reset_n => clock_0_out_reset_n,
      clock_0_out_waitrequest => clock_0_out_waitrequest,
      VGA_avalon_character_slave_readdata_from_sa => VGA_avalon_character_slave_readdata_from_sa,
      clk => clk,
      clock_0_out_address => clock_0_out_address,
      clock_0_out_granted_VGA_avalon_character_slave => clock_0_out_granted_VGA_avalon_character_slave,
      clock_0_out_qualified_request_VGA_avalon_character_slave => clock_0_out_qualified_request_VGA_avalon_character_slave,
      clock_0_out_read => clock_0_out_read,
      clock_0_out_read_data_valid_VGA_avalon_character_slave => clock_0_out_read_data_valid_VGA_avalon_character_slave,
      clock_0_out_requests_VGA_avalon_character_slave => clock_0_out_requests_VGA_avalon_character_slave,
      clock_0_out_write => clock_0_out_write,
      clock_0_out_writedata => clock_0_out_writedata,
      d1_VGA_avalon_character_slave_end_xfer => d1_VGA_avalon_character_slave_end_xfer,
      reset_n => clk_reset_n
    );


  --the_clock_0, which is an e_ptf_instance
  the_clock_0 : clock_0
    port map(
      master_address => clock_0_out_address,
      master_byteenable => clock_0_out_byteenable,
      master_nativeaddress => clock_0_out_nativeaddress,
      master_read => clock_0_out_read,
      master_write => clock_0_out_write,
      master_writedata => clock_0_out_writedata,
      slave_endofpacket => clock_0_in_endofpacket,
      slave_readdata => clock_0_in_readdata,
      slave_waitrequest => clock_0_in_waitrequest,
      master_clk => clk,
      master_endofpacket => clock_0_out_endofpacket,
      master_readdata => clock_0_out_readdata,
      master_reset_n => clock_0_out_reset_n,
      master_waitrequest => clock_0_out_waitrequest,
      slave_address => clock_0_in_address,
      slave_byteenable => clock_0_in_byteenable,
      slave_clk => internal_clk_90,
      slave_nativeaddress => clock_0_in_nativeaddress,
      slave_read => clock_0_in_read,
      slave_reset_n => clock_0_in_reset_n,
      slave_write => clock_0_in_write,
      slave_writedata => clock_0_in_writedata
    );


  --the_clock_1_in, which is an e_instance
  the_clock_1_in : clock_1_in_arbitrator
    port map(
      CPU_data_master_granted_clock_1_in => CPU_data_master_granted_clock_1_in,
      CPU_data_master_qualified_request_clock_1_in => CPU_data_master_qualified_request_clock_1_in,
      CPU_data_master_read_data_valid_clock_1_in => CPU_data_master_read_data_valid_clock_1_in,
      CPU_data_master_requests_clock_1_in => CPU_data_master_requests_clock_1_in,
      clock_1_in_address => clock_1_in_address,
      clock_1_in_byteenable => clock_1_in_byteenable,
      clock_1_in_endofpacket_from_sa => clock_1_in_endofpacket_from_sa,
      clock_1_in_nativeaddress => clock_1_in_nativeaddress,
      clock_1_in_read => clock_1_in_read,
      clock_1_in_readdata_from_sa => clock_1_in_readdata_from_sa,
      clock_1_in_reset_n => clock_1_in_reset_n,
      clock_1_in_waitrequest_from_sa => clock_1_in_waitrequest_from_sa,
      clock_1_in_write => clock_1_in_write,
      clock_1_in_writedata => clock_1_in_writedata,
      d1_clock_1_in_end_xfer => d1_clock_1_in_end_xfer,
      CPU_data_master_address_to_slave => CPU_data_master_address_to_slave,
      CPU_data_master_byteenable => CPU_data_master_byteenable,
      CPU_data_master_read => CPU_data_master_read,
      CPU_data_master_waitrequest => CPU_data_master_waitrequest,
      CPU_data_master_write => CPU_data_master_write,
      CPU_data_master_writedata => CPU_data_master_writedata,
      clk => internal_clk_90,
      clock_1_in_endofpacket => clock_1_in_endofpacket,
      clock_1_in_readdata => clock_1_in_readdata,
      clock_1_in_waitrequest => clock_1_in_waitrequest,
      reset_n => clk_90_reset_n
    );


  --the_clock_1_out, which is an e_instance
  the_clock_1_out : clock_1_out_arbitrator
    port map(
      clock_1_out_address_to_slave => clock_1_out_address_to_slave,
      clock_1_out_readdata => clock_1_out_readdata,
      clock_1_out_reset_n => clock_1_out_reset_n,
      clock_1_out_waitrequest => clock_1_out_waitrequest,
      PLL_s1_readdata_from_sa => PLL_s1_readdata_from_sa,
      clk => clk,
      clock_1_out_address => clock_1_out_address,
      clock_1_out_granted_PLL_s1 => clock_1_out_granted_PLL_s1,
      clock_1_out_qualified_request_PLL_s1 => clock_1_out_qualified_request_PLL_s1,
      clock_1_out_read => clock_1_out_read,
      clock_1_out_read_data_valid_PLL_s1 => clock_1_out_read_data_valid_PLL_s1,
      clock_1_out_requests_PLL_s1 => clock_1_out_requests_PLL_s1,
      clock_1_out_write => clock_1_out_write,
      clock_1_out_writedata => clock_1_out_writedata,
      d1_PLL_s1_end_xfer => d1_PLL_s1_end_xfer,
      reset_n => clk_reset_n
    );


  --the_clock_1, which is an e_ptf_instance
  the_clock_1 : clock_1
    port map(
      master_address => clock_1_out_address,
      master_byteenable => clock_1_out_byteenable,
      master_nativeaddress => clock_1_out_nativeaddress,
      master_read => clock_1_out_read,
      master_write => clock_1_out_write,
      master_writedata => clock_1_out_writedata,
      slave_endofpacket => clock_1_in_endofpacket,
      slave_readdata => clock_1_in_readdata,
      slave_waitrequest => clock_1_in_waitrequest,
      master_clk => clk,
      master_endofpacket => clock_1_out_endofpacket,
      master_readdata => clock_1_out_readdata,
      master_reset_n => clock_1_out_reset_n,
      master_waitrequest => clock_1_out_waitrequest,
      slave_address => clock_1_in_address,
      slave_byteenable => clock_1_in_byteenable,
      slave_clk => internal_clk_90,
      slave_nativeaddress => clock_1_in_nativeaddress,
      slave_read => clock_1_in_read,
      slave_reset_n => clock_1_in_reset_n,
      slave_write => clock_1_in_write,
      slave_writedata => clock_1_in_writedata
    );


  --reset is asserted asynchronously and deasserted synchronously
  NIOS_II_reset_clk_domain_synch : NIOS_II_reset_clk_domain_synch_module
    port map(
      data_out => clk_reset_n,
      clk => clk,
      data_in => module_input8,
      reset_n => reset_n_sources
    );

  module_input8 <= std_logic'('1');

  --clk_90 assignment, which is an e_assign
  internal_clk_90 <= out_clk_PLL_c0;
  --clk_25 assignment, which is an e_assign
  internal_clk_25 <= out_clk_PLL_c1;
  --clk_25_180 assignment, which is an e_assign
  clk_25_180 <= out_clk_PLL_c2;
  --clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_0_out_endofpacket <= std_logic'('0');
  --clock_1_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_1_out_endofpacket <= std_logic'('0');
  --vhdl renameroo for output signals
  LCD_E_from_the_LCD <= internal_LCD_E_from_the_LCD;
  --vhdl renameroo for output signals
  LCD_RS_from_the_LCD <= internal_LCD_RS_from_the_LCD;
  --vhdl renameroo for output signals
  LCD_RW_from_the_LCD <= internal_LCD_RW_from_the_LCD;
  --vhdl renameroo for output signals
  VGA_BLANK_from_the_VGA <= internal_VGA_BLANK_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_B_from_the_VGA <= internal_VGA_B_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_G_from_the_VGA <= internal_VGA_G_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_HS_from_the_VGA <= internal_VGA_HS_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_R_from_the_VGA <= internal_VGA_R_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_SYNC_from_the_VGA <= internal_VGA_SYNC_from_the_VGA;
  --vhdl renameroo for output signals
  VGA_VS_from_the_VGA <= internal_VGA_VS_from_the_VGA;
  --vhdl renameroo for output signals
  address_from_the_AVALON <= internal_address_from_the_AVALON;
  --vhdl renameroo for output signals
  bus_enable_from_the_AVALON <= internal_bus_enable_from_the_AVALON;
  --vhdl renameroo for output signals
  byte_enable_from_the_AVALON <= internal_byte_enable_from_the_AVALON;
  --vhdl renameroo for output signals
  clk_25 <= internal_clk_25;
  --vhdl renameroo for output signals
  clk_90 <= internal_clk_90;
  --vhdl renameroo for output signals
  rw_from_the_AVALON <= internal_rw_from_the_AVALON;
  --vhdl renameroo for output signals
  txd_from_the_IRDA <= internal_txd_from_the_IRDA;
  --vhdl renameroo for output signals
  write_data_from_the_AVALON <= internal_write_data_from_the_AVALON;
  --vhdl renameroo for output signals
  zs_addr_from_the_SDRAM <= internal_zs_addr_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_ba_from_the_SDRAM <= internal_zs_ba_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_cas_n_from_the_SDRAM <= internal_zs_cas_n_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_cke_from_the_SDRAM <= internal_zs_cke_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_cs_n_from_the_SDRAM <= internal_zs_cs_n_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_dqm_from_the_SDRAM <= internal_zs_dqm_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_ras_n_from_the_SDRAM <= internal_zs_ras_n_from_the_SDRAM;
  --vhdl renameroo for output signals
  zs_we_n_from_the_SDRAM <= internal_zs_we_n_from_the_SDRAM;

end europa;


--synthesis translate_off

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your libraries here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

entity test_bench is 
end entity test_bench;


architecture europa of test_bench is
component NIOS_II is 
           port (
                 -- 1) global signals:
                    signal clk : IN STD_LOGIC;
                    signal clk_25 : OUT STD_LOGIC;
                    signal clk_25_180 : OUT STD_LOGIC;
                    signal clk_90 : OUT STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- the_AVALON
                    signal acknowledge_to_the_AVALON : IN STD_LOGIC;
                    signal address_from_the_AVALON : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal bus_enable_from_the_AVALON : OUT STD_LOGIC;
                    signal byte_enable_from_the_AVALON : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal irq_to_the_AVALON : IN STD_LOGIC;
                    signal read_data_to_the_AVALON : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal rw_from_the_AVALON : OUT STD_LOGIC;
                    signal write_data_from_the_AVALON : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- the_IRDA
                    signal rxd_to_the_IRDA : IN STD_LOGIC;
                    signal txd_from_the_IRDA : OUT STD_LOGIC;

                 -- the_KEYS
                    signal in_port_to_the_KEYS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- the_LCD
                    signal LCD_E_from_the_LCD : OUT STD_LOGIC;
                    signal LCD_RS_from_the_LCD : OUT STD_LOGIC;
                    signal LCD_RW_from_the_LCD : OUT STD_LOGIC;
                    signal LCD_data_to_and_from_the_LCD : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- the_SDRAM
                    signal zs_addr_from_the_SDRAM : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
                    signal zs_ba_from_the_SDRAM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_cas_n_from_the_SDRAM : OUT STD_LOGIC;
                    signal zs_cke_from_the_SDRAM : OUT STD_LOGIC;
                    signal zs_cs_n_from_the_SDRAM : OUT STD_LOGIC;
                    signal zs_dq_to_and_from_the_SDRAM : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal zs_dqm_from_the_SDRAM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_ras_n_from_the_SDRAM : OUT STD_LOGIC;
                    signal zs_we_n_from_the_SDRAM : OUT STD_LOGIC;

                 -- the_SWITCHES
                    signal in_port_to_the_SWITCHES : IN STD_LOGIC_VECTOR (17 DOWNTO 0);

                 -- the_VGA
                    signal VGA_BLANK_from_the_VGA : OUT STD_LOGIC;
                    signal VGA_B_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_G_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_HS_from_the_VGA : OUT STD_LOGIC;
                    signal VGA_R_from_the_VGA : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal VGA_SYNC_from_the_VGA : OUT STD_LOGIC;
                    signal VGA_VS_from_the_VGA : OUT STD_LOGIC
                 );
end component NIOS_II;

component SDRAM_test_component is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal zs_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                    signal zs_ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_cas_n : IN STD_LOGIC;
                    signal zs_cke : IN STD_LOGIC;
                    signal zs_cs_n : IN STD_LOGIC;
                    signal zs_dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal zs_ras_n : IN STD_LOGIC;
                    signal zs_we_n : IN STD_LOGIC;

                 -- outputs:
                    signal zs_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component SDRAM_test_component;

                signal IRDA_s1_dataavailable_from_sa :  STD_LOGIC;
                signal IRDA_s1_readyfordata_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_dataavailable_from_sa :  STD_LOGIC;
                signal JTAG_avalon_jtag_slave_readyfordata_from_sa :  STD_LOGIC;
                signal KEYS_s1_irq :  STD_LOGIC;
                signal LCD_E_from_the_LCD :  STD_LOGIC;
                signal LCD_RS_from_the_LCD :  STD_LOGIC;
                signal LCD_RW_from_the_LCD :  STD_LOGIC;
                signal LCD_control_slave_irq :  STD_LOGIC;
                signal LCD_data_to_and_from_the_LCD :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal VGA_BLANK_from_the_VGA :  STD_LOGIC;
                signal VGA_B_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal VGA_G_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal VGA_HS_from_the_VGA :  STD_LOGIC;
                signal VGA_R_from_the_VGA :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal VGA_SYNC_from_the_VGA :  STD_LOGIC;
                signal VGA_VS_from_the_VGA :  STD_LOGIC;
                signal acknowledge_to_the_AVALON :  STD_LOGIC;
                signal address_from_the_AVALON :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal bus_enable_from_the_AVALON :  STD_LOGIC;
                signal byte_enable_from_the_AVALON :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clk :  STD_LOGIC;
                signal clk_25 :  STD_LOGIC;
                signal clk_25_180 :  STD_LOGIC;
                signal clk_90 :  STD_LOGIC;
                signal clock_0_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_0_out_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal clock_0_out_endofpacket :  STD_LOGIC;
                signal clock_0_out_nativeaddress :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal clock_1_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_1_out_byteenable :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_endofpacket :  STD_LOGIC;
                signal in_port_to_the_KEYS :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal in_port_to_the_SWITCHES :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal irq_to_the_AVALON :  STD_LOGIC;
                signal read_data_to_the_AVALON :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal reset_n :  STD_LOGIC;
                signal rw_from_the_AVALON :  STD_LOGIC;
                signal rxd_to_the_IRDA :  STD_LOGIC;
                signal txd_from_the_IRDA :  STD_LOGIC;
                signal write_data_from_the_AVALON :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal zs_addr_from_the_SDRAM :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal zs_ba_from_the_SDRAM :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal zs_cas_n_from_the_SDRAM :  STD_LOGIC;
                signal zs_cke_from_the_SDRAM :  STD_LOGIC;
                signal zs_cs_n_from_the_SDRAM :  STD_LOGIC;
                signal zs_dq_to_and_from_the_SDRAM :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal zs_dqm_from_the_SDRAM :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal zs_ras_n_from_the_SDRAM :  STD_LOGIC;
                signal zs_we_n_from_the_SDRAM :  STD_LOGIC;


-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your component and signal declaration here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>


begin

  --Set us up the Dut
  DUT : NIOS_II
    port map(
      LCD_E_from_the_LCD => LCD_E_from_the_LCD,
      LCD_RS_from_the_LCD => LCD_RS_from_the_LCD,
      LCD_RW_from_the_LCD => LCD_RW_from_the_LCD,
      LCD_data_to_and_from_the_LCD => LCD_data_to_and_from_the_LCD,
      VGA_BLANK_from_the_VGA => VGA_BLANK_from_the_VGA,
      VGA_B_from_the_VGA => VGA_B_from_the_VGA,
      VGA_G_from_the_VGA => VGA_G_from_the_VGA,
      VGA_HS_from_the_VGA => VGA_HS_from_the_VGA,
      VGA_R_from_the_VGA => VGA_R_from_the_VGA,
      VGA_SYNC_from_the_VGA => VGA_SYNC_from_the_VGA,
      VGA_VS_from_the_VGA => VGA_VS_from_the_VGA,
      address_from_the_AVALON => address_from_the_AVALON,
      bus_enable_from_the_AVALON => bus_enable_from_the_AVALON,
      byte_enable_from_the_AVALON => byte_enable_from_the_AVALON,
      clk_25 => clk_25,
      clk_25_180 => clk_25_180,
      clk_90 => clk_90,
      rw_from_the_AVALON => rw_from_the_AVALON,
      txd_from_the_IRDA => txd_from_the_IRDA,
      write_data_from_the_AVALON => write_data_from_the_AVALON,
      zs_addr_from_the_SDRAM => zs_addr_from_the_SDRAM,
      zs_ba_from_the_SDRAM => zs_ba_from_the_SDRAM,
      zs_cas_n_from_the_SDRAM => zs_cas_n_from_the_SDRAM,
      zs_cke_from_the_SDRAM => zs_cke_from_the_SDRAM,
      zs_cs_n_from_the_SDRAM => zs_cs_n_from_the_SDRAM,
      zs_dq_to_and_from_the_SDRAM => zs_dq_to_and_from_the_SDRAM,
      zs_dqm_from_the_SDRAM => zs_dqm_from_the_SDRAM,
      zs_ras_n_from_the_SDRAM => zs_ras_n_from_the_SDRAM,
      zs_we_n_from_the_SDRAM => zs_we_n_from_the_SDRAM,
      acknowledge_to_the_AVALON => acknowledge_to_the_AVALON,
      clk => clk,
      in_port_to_the_KEYS => in_port_to_the_KEYS,
      in_port_to_the_SWITCHES => in_port_to_the_SWITCHES,
      irq_to_the_AVALON => irq_to_the_AVALON,
      read_data_to_the_AVALON => read_data_to_the_AVALON,
      reset_n => reset_n,
      rxd_to_the_IRDA => rxd_to_the_IRDA
    );


  --the_SDRAM_test_component, which is an e_instance
  the_SDRAM_test_component : SDRAM_test_component
    port map(
      zs_dq => zs_dq_to_and_from_the_SDRAM,
      clk => clk_90,
      zs_addr => zs_addr_from_the_SDRAM,
      zs_ba => zs_ba_from_the_SDRAM,
      zs_cas_n => zs_cas_n_from_the_SDRAM,
      zs_cke => zs_cke_from_the_SDRAM,
      zs_cs_n => zs_cs_n_from_the_SDRAM,
      zs_dqm => zs_dqm_from_the_SDRAM,
      zs_ras_n => zs_ras_n_from_the_SDRAM,
      zs_we_n => zs_we_n_from_the_SDRAM
    );


  process
  begin
    clk <= '0';
    loop
       wait for 10 ns;
       clk <= not clk;
    end loop;
  end process;
  PROCESS
    BEGIN
       reset_n <= '0';
       wait for 200 ns;
       reset_n <= '1'; 
    WAIT;
  END PROCESS;


-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add additional architecture here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>


end europa;



--synthesis translate_on
